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US 7,247,930 B2Granted
Power management integrated circuit
AssigneeIntel Corporation
InventorsSiva G. Narendra, James W. Tschantz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
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Abstract
A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a power management die bonded to the CPU die in a three dimensional packaging layout.
Claims17
A central processing unit (CPU) comprising:
- a CPU die;
- and
- a power management die having a metal side surface bonded to a metal side surface of the CPU die in a three dimensional assembly.
A method comprising bonding a metal side surface of a power management die to a metal side surface of a central processing unit (CPU) die in a three-dimensional assembly.
A system comprising:
- a central processing unit (CPU) having:
- a CPU die;
- and
- a power management die having a metal side surface bonded to a metal side surface of the CPU die in a three dimensional assembly;
- a chipset coupled to the CPU;
- and
- a main memory device coupled to the chipset.
4 more elements
Dependencies are inferred from the claim text.