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US 7,247,919 B1Granted
Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxides MOSFETs
AssigneeMicron Technology, Inc.
InventorsChandra V. Mouli, Ceredig Roberts
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Abstract
An integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region and a gate oxide layer is provided on the active regions. A gate electrode is provided upon the gate oxide layer wherein beneath an edge of the gate electrode, a gate-drain overlap region having a high dose ion implant is provided.
Claims22
A circuit structure comprising:
- a semiconductor layer;
- an oxide layer formed on said semiconductor layer, the entire said oxide layer having a substantially uniform thickness;
- a gate structure formed on a portion of said oxide layer and having first and second leading edges, said oxide layer extends outwardly from both said leading edges of said gate structure;
- and
- a first overlap region of the oxide layer located only beneath said gate structure and adjacent said first leading edge and inward of said second leading edge, and a second overlap region comprising all remaining portions of the oxide layer located beneath said gate structure, said second overlap region having first and second sides, said first side being adjacent said first overlap region and said second side being adjacent said second leading edge, said first overlap region having a predetermined ion implant concentration higher than in said second overlap region and all remaining oxide layer portions extending outwardly from both said first and second leading edges of said gate structure, said predetermined implant concentration being sufficient to increase the electrical gate oxide thickness in said overlap region, and wherein said predetermined ion implant concentration is about 1E18 atoms per cubic centimeter of fluorine.
2 more elements
A circuit structure comprising:
- a semiconductor layer;
- a source region and a drain region in said semiconductor layer which are lightly doped with a first conductivity-type dopant;
- a channel region located between said source/drain regions;
- a gate oxide layer located on a surface of said channel region, the entire said gate oxide layer having a substantially uniform thickness;
- and
- a gate electrode located on said gate oxide layer above said channel region, said gate oxide layer extends outwardly from both sides of said gate electrode, wherein portions of said gate oxide layer located only under said gate electrode include a first overlap region and a second overlap region, said first overlap region is inward of said source region and adjacent said drain region, said second overlap region includes all remaining portions of said gate oxide layer under said gate electrode and has first and second sides, said first side is adjacent said source region and said second side is adjacent said first overlap region, said first overlap region having an ion implant concentration higher than in said second overlap region and all remaining portions of said oxide layer extending outwardly from both said sides of the gate electrode, which is effective to lower the surface electrical field in said overlap region, and wherein said ion implant concentration is about 1E18 atoms per cubic centimeter of fluorine.
3 more elements
A circuit structure comprising:
- a semiconductor layer;
- a first dopant-type MOS transistor is situated on said semiconductor layer having:
- a source region and a drain region in said semiconductor layer which are doped with a first conductivity-type dopant;
- a channel region located between said source/drain regions;
- a gate oxide layer located on a surface of said channel region, the entire said gate oxide layer having a substantially uniform thickness;
- a gate electrode located on said gate oxide layer above said channel region, said gate oxide layer extends outwardly from both sides of said gate electrode, wherein portions of said gate oxide layer located only under said gate electrode include a first overlap region and a second overlap region, said first overlap region is inward of said source region and adjacent said drain region, said second overlap region includes all remaining portions of said gate oxide layer under said gate electrode and has first and second sides, said first side is adjacent said first overlap region and said second side is adjacent said source region, said first overlap region having an ion implant concentration higher than in said second overlap region and all remaining portions of said gate oxide layer extending outwardly from both said sides of the gate electrode, which is effective to lower the surface electrical field in said overlap region;
- and,
- a second-type dopant MOS transistor which is complementary to said first dopant-type MOS transistor, said second-type dopant MOS transistor is situated on said semiconductor layer and includes a second gate oxide layer, two complementary source/drain regions which are doped with a second conductivity-type dopant, and a complementary gate electrode located on said second gate oxide layer, and wherein said ion implant concentration is about 1E18 atoms per cubic centimeter of fluorine.
5 more elements
A circuit structure comprising:
- a semiconductor layer having a source region, a drain region, and a channel region located between said source/drain regions;
- a gate oxide layer located at least on a surface of said channel region, the entire said gate oxide layer having a substantially uniform thickness;
- and
- a gate electrode located on a portion of said gate oxide layer above said channel region, said gate oxide layer extends outwardly from both sides of said gate electrode, wherein the portion of said gate oxide layer located only beneath said gate electrode has first and second portions, said first portion is adjacent said drain region, said second portion comprises all remaining portions of said gate oxide layer located under said gate electrode and has first and second sides, said first side is adjacent said first portion and said second side is adjacent said source region, and said first portion has a higher ion implant concentration than in said second portion and all remaining portions of said gate oxide layer extending outwardly from both said sides of said gate electrode, and wherein said ion implant concentration is about 1E18 atoms per cubic centimeter of fluorine.
1 more element
A circuit structure comprising:
- a semiconductor layer having a pair of field isolation regions and a channel region, said channel region is located between said pair of field isolation regions;
- a gate oxide layer located at least on a surface of said channel region, the entire said gate oxide layer having a substantially uniform thickness;
- and
- a gate electrode located on said gate oxide layer above said channel region, said gate oxide layer extends outwardly from both sides of said gate electrode, wherein portions of said gate oxide layer located only beneath said gate electrode include a first portion and a second portion, said first portion is adjacent a first one of said pair of field isolation regions, said second portion comprises all remaining portions of said gate oxide layer under said gate electrode and has first and second sides, said first side is adjacent said first portion and said second side is adjacent a second one of said pair of field isolation regions, and said first portion has a higher ion implant concentration than in said second portion and all remaining portions of said gate oxide layer between said pair of field isolation regions, and wherein said ion implant concentration is about 1E18 atoms per cubic centimeter of fluorine.
1 more element
Dependencies are inferred from the claim text.