Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing

An array of NAND flash memory structures, said array comprising:

• a semiconductor substrate of a first conductivity type;
• a plurality of NAND structure, each structure comprising:
• a first region of a second conductivity type in said substrate;
• a second region of the second conductivity type in said substrate, spaced apart from said first region, in a first direction, thereby defining a channel region therebetween;
• a plurality of floating gates, spaced apart from one another, each insulated from the channel region;
• a plurality of control gates, spaced apart from one another, each insulated from the channel region, each control gate being between a pair of floating gates and being capacitively coupled to said pair of floating gates;
• a plurality of select gates, spaced apart from one another, each insulated from the channel region, each select gate being between a pair of floating gates;
• and
• wherein NAND structures adjacent to one another in a second direction, substantially perpendicular to the first direction have the select gate connected to one another in the second direction, and the control gate connected to one another in the second direction.