US 7,247,905 B2Granted

Offset vertical device

AssigneeInternational Business Machines Corporation

InventorsKangguo Cheng, Ramachandra Divakaruni, Geng Wang

Life of this patent

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Abstract

The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.

Claims11

Dependent claims

A memory array comprising:

at least one first-type memory device, each of said at least one first-type memory device comprising a first transistor, a first underlying capacitor, a first buried strap, and a first collar region with a first vertical length which is substantially constant throughout the periphery of said first collar region, wherein said first buried strap is located at a first depth and is positioned on said first collar region and is in electrical contact with both said first transistor and said first underlying capacitor;
and
at least one second-type memory device, each of said at least one second-type memory device comprising a second transistor, a second underlying capacitor, an offset buried strap, and a second collar region with a second vertical length which is substantially constant throughout the periphery of said second collar region, wherein said offset buried strap is located at a second depth that is different from said first depth and is positioned on said second collar region and is in electrical contact with both said second transistor and said second underlying capacitor, and said second vertical length is equal to said first vertical length.

Dependencies are inferred from the claim text.

Facts

Application: 10/813,352Filed 30 Mar 2004
Published: US 2005/0224852 A113 Oct 2005
Granted: 24 Jul 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 12/0385
The capacitor being in a trench in the substrate: making a connection between the transistor and the capacitor, e.g. buried strap
H10B 12/0387
The capacitor being in a trench in the substrate: making the trench
H10D 1/047
Of capacitors having potential barriers, e.g. varactors: of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
H10D 1/665
Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors: trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors