Three dimensional programmable device and method for fabricating the same
AssigneeIntel Corporation
InventorTyler A. Lowrey
Life of this patent
Estimating the term…
Abstract
A three-dimensional memory device having polycrystalline silicon diode isolation elements for phase change memory cells and method for fabricating the same. The memory device includes a plurality of stacked memory cells to form a three-dimensional memory array. The polycrystalline silicon diode element selects the phase change memory cell. The memory device is fabricated by forming a plurality of phase change memory cells and diode isolation elements on a base layer. Additional layers of memory cells and isolation elements are formed over the initial layer.
Claims16
An apparatus comprising:
- at least two stacked planes over a circuit level substrate, each of said planes including individual programmable cells, a cell in each plane comprising a chalcogenide material;
- at least one contact;
- and
- a U-shaped electrode coupled to the material and disposed under the material and between the material and the at least one contact, the electrode comprising at least a base and a first and second upstanding portion connected by said base, said first upstanding portion having a different resistance than said second upstanding portion.
A memory device comprising:
- a plurality of programmable cells in a stacked configuration on a circuit level substrate, each of the plurality of programmable cells comprising a chalcogenide material disposed between a first contact and a second contact, the material coupled to one of the first contact and the second contact by a U-shaped electrode comprising at least a base and a first and second upstanding portion connected by said base, said first upstanding portion having a different resistance than said second upstanding portion,
- wherein at least one of the first contact and the second contact is shared between adjacent programmable cells.
An apparatus comprising:
- a bus;
- a processor coupled to the bus;
- a wireless interface coupled to the bus;
- a memory device including at least two stacked planes over a circuit level substrate, each plane including a individual programmable cell, a cell in each plane comprising a chalcogenide material;
- at least contact;
- and
- a U-shaped electrode coupled to the volume of programmable material, and disposed between to volume of programmable material and the at least one contact, the electrode comprising a first and second upstanding portion connected by a base, said first upstanding portion having a different resistance than said second upstanding portion.
Dependencies are inferred from the claim text.