Reduction in size of column sample and hold circuitry in a CMOS imager

An integrated circuit, comprising:

• an array comprised of a plurality of columns and rows;
• a plurality of sensing circuits at least a top of the array, wherein each sensing circuit comprises a plurality of pairs of first and second capacitors, wherein the plurality of pairs of first and second capacitors in each sensing circuit are vertically stacked above a plurality of columns to which they are coupled in a direction parallel to the plurality of columns.

A method for optimizing a sample and hold circuit for an imager integrated circuit, wherein the sample and hold circuit comprises a plurality of pairs of sampling and reference capacitors vertically stacked over a plurality of array columns served by those pairs in a direction parallel to the columns, the method implementable on a computer, the method comprising:

• entering a plurality of design constraints into the computer relevant to the design of the sampling and reference capacitors in the sample and hold circuit;
• processing the plurality of design constraints using the computer to determine an optimal form factor n, wherein n comprises the number of the plurality of pairs of sampling and reference capacitors vertically stacked over the plurality of array columns served by those pairs, wherein the optimal form factor n comprises a value that minimizes the column height of the sample and hold circuit, wherein the column height comprises a height of the vertical stack of the plurality of pairs of sampling and reference capacitors in a direction parallel to the columns.

A method for designing a sample and hold circuit for an imager integrated circuit, wherein the sample and hold circuit comprises a plurality of pairs of sampling and reference capacitors vertically stacked over a plurality of array columns serviced by those pairs in a direction parallel to the columns, the method comprising:

• providing a plurality of design constraints relevant to the design of the sampling and reference capacitors in the sample and hold circuit;
• determining an optimal form factor n using the plurality of design constraints, wherein n comprises the number of the plurality of pairs of sampling and reference capacitors vertically stacked over the plurality of array columns served by those pairs, wherein the optimal form factor yields a smallest column height of the vertically stacked pairs of sampling and reference capacitors in a direction parallel to the columns;
• using a computer to create layout data for the sampling and reference capacitors in accordance with the determined optimal form factor n and in accordance with the plurality of design constraints, wherein the layout data is used in the fabrication of masks used to fabricate the imager integrated circuit.