Integrated circuit having structural support for a flip-chip interconnect pad and method therefor

A method of making an integrated circuit, comprising:

• providing a circuit design having a layout comprising:
• a substrate having active circuitry;
• a stack of interconnect layers for interconnecting the active circuitry;
• a plurality of interlayer dielectrics for insulating the interconnect layers of the stack of interconnect layers and for connecting the interconnect layers of the stack of interconnect layers with vias;
• a bond pad overlying the stack of interconnect layers and the plurality of interlayer dielectrics, at least one underlying interconnect layer of the stack of interconnect layers not being electrically connected to the bond pad and being used for wiring or interconnect other than directly to the bond pad;
• defining a force region at least under the bond pad;
• determining which interconnect layers of the stack of interconnect layers have a metal density that is a less than a predetermined percentage;
• obtaining a modified design by adding dummy metal lines to the interconnect layers of the stack of interconnect layers that were determined to have less than the predetermined percentage sufficient to raise the metal density to at least the predetermined percentage;
• and
• making the integrated circuit according to the modified design.

A method of making an integrated circuit having a plurality of bond pads, comprising:

• developing a circuit design of the integrated circuit;
• developing a layout of the integrated circuit according to the circuit design, wherein the layout comprises a plurality of interconnect layers underlying a first bond pad of the plurality of bond pads, at least one of the plurality of interconnect layers not being electrically connected to the first bond pad and used for wiring or interconnect other than directly to the first bond pad;
• defining a force region at least under the first bond pad of the plurality of bond pads, wherein the force region comprises a first portion of each of the plurality of interconnect layers;
• identifying a first interconnect layer of the plurality of interconnect layers in which the first portion of the first interconnect layer has a metal density below a predetermined percentage;
• modifying the layout by adding dummy metal lines to the first portion of the first interconnect layer to increase the metal density of the first portion of the first interconnect layer;
• and
• making the integrated circuit comprising the dummy metal lines.

A method of making an integrated circuit having a plurality of bond pads, comprising:

• developing a circuit design of the integrated circuit;
• developing a layout of the integrated circuit according to the circuit design, wherein the layout comprises a plurality of metal-containing interconnect layers that extend under a first bond pad of the plurality of bond pads, at least a portion of the plurality of metal-containing interconnect layers underlying the first bond pad and not electrically connected to the first bond pad as a result of being used for electrical interconnection not directly connected to the bond pad;
• modifying the layout by adding dummy metal lines to the plurality of metal-containing interconnect layers to achieve a metal density of at least forty percent for each of the plurality of metal-containing interconnect layers;
• and
• forming the integrated circuit comprising the dummy metal lines.