Methods of forming field effect transistors having recessed channel regions

A method of forming an insulated-gate field effect transistor having a recessed channel region, comprising:

• forming a first electrically insulating layer on a surface of a semiconductor active region;
• patterning the first electrically insulating layer to define a plurality of openings therein that extend opposite the semiconductor active region;
• forming a trench mask having a second plurality of openings therein by filling the first plurality of openings with electrically insulating plugs and then etching the patterned first electrically insulating layer using the electrically insulating plugs as an etching mask;
• forming a plurality of trenches in the active region by etching the semiconductor active region using the trench mask as an etching mask;
• and
• forming a plurality of insulated gate electrodes that extend into the plurality of trenches.

A method of forming an insulated-gate field effect transistor having a trench-based gate electrode, comprising:

• forming a first electrically insulating layer on a surface of a semiconductor active region;
• patterning the first electrically insulating layer to define a plurality of openings therein that extend opposite the semiconductor active region;
• depositing a second electrically insulating layer that extends on the patterned first electrically insulating layer and into the plurality of openings;
• planarizing the second electrically insulating layer to define a plurality of electrically insulating plugs in the plurality of openings;
• forming a plurality of trenches in the semiconductor active region by etching the patterned first electrically insulating layer and the semiconductor active region in sequence using the plurality of electrically insulating plugs as an etching mask;
• and
• forming a plurality of insulated gate electrodes that extend into the plurality of trenches.