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US 7,247,535 B2Granted
Source/drain extensions having highly activated and extremely abrupt junctions
AssigneeTexas Instruments Incorporated
InventorAmitabh Jain
Life of this patent
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Abstract
A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. Also, a transistor source/drain region 80, 90 having a SiGe source/drain extension 90 that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.
Claims21
A method for making a transistor within a semiconductor wafer, comprising:
- forming a gate stack, said gate stack having a gate silicon oxide layer coupled to said semiconductor wafer and a gate polysilicon layer coupled to said gate silicon oxide layer;
- forming source/drain extension sidewall spacers coupled to said gate stack;
- forming deep source/drain sidewall spacers coupled to said source/drain extension sidewall spacers;
- implanting dopants into said semiconductor wafer at deep source/drain locations;
- removing said deep source/drain sidewall spacers;
- reshaping said source/drain extension sidewall spacers;
- etching a recess in a surface of said semiconductor wafer at source/drain extension locations;
- depositing SiGe within each said recess to form SiGe source/drain extensions;
- implanting dopants into said SiGe source/drain extensions;
- and
- performing a first post extension implant anneal of said semiconductor wafer.
8 more elements
Dependencies are inferred from the claim text.