Method for manufacturing a semiconductor device
AssigneeRenesas Technology Corp.
InventorsJun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
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AssigneeRenesas Technology Corp.
InventorsJun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
Estimating the term…
As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.
A method for manufacturing a semiconductor device comprising the steps of:
A method for manufacturing a semiconductor device comprising the steps of, (1) forming a first conductor layer having a first, a second and a third insulation layer above a substrate in order, (2) removing said third insulation layer to form an opening, (3) forming a second conductor layer having a second and a third insulation layer over said third insulation layer of said first conductor layer, (4) selectively removing said third and said second insulation layer of second conductor layer and then removing said second and said first insulation layer of first conductor layer to form a wiring trench which extends through the layers to reach said substrate, (5) depositing a conductive film to cover an internal wall of said wiring trench and then burying copper inside said wiring trench to form a wiring layer, (6) removing said third insulation layer of the second conductor layer as to expose a surface of said second insulation layer of the second conductor layer and to produce a dual-damascene structure, and (7) repeating steps (1)–(6), wherein a second insulation layer of a conductor layer positioned at a lower-layer part among said conductor layers is formed to have a dielectric constant smaller than that of a second insulation layer of a conductor layer positioned at an upper-layer part among said conductor layers.
Dependencies are inferred from the claim text.