US 7,247,516 B1 · Method for fabricating a leadless chip carrier

Abstract

Structure and method for fabrication of a leadless chip carrier have been disclosed. A disclosed embodiment comprises a substrate having a top surface for receiving a semiconductor die. The disclosed embodiment also comprises a printed circuit board attached to a bottom surface of the substrate. The disclosed embodiment further comprises at least one via in the substrate, which provides an electrical connection between a signal bond pad of the semiconductor die and the printed circuit board. The at least one via also electrically connects a substrate bond pad and the printed circuit board. The substrate bond pad is further connected to the signal bond pad of the semiconductor die by a signal bonding wire. The at least one via further provides an electrical connection between the signal bond pad of the semiconductor die and a land that is electrically connected to the printed circuit board.

Claims16

Dependent claims

A method for fabricating a structure for receiving a semiconductor die, said method comprising steps of:

drilling a first hole in a substrate;
filling said first hole with metal to form a first via;
patterning a support pad on a top surface of said substrate, and patterning a heat spreader on a bottom surface of said substrate, said first via providing an electrical connection between said heat spreader and said support pad, said support pad being suitable for receiving said semiconductor die.

Dependencies are inferred from the claim text.

Facts

Application

11/256,511Filed 21 Oct 2005 · division

Priority

15 Nov 2000

Granted

24 Jul 2007

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10W 70/095
Of insulating or insulated package substrates, or of interposers, or of redistribution layers: of vias therein
H10W 40/228
Characterised by projecting parts, e.g. fins to increase surface area: the projecting parts being wire-shaped or pin-shaped
H10W 70/05
Manufacture or treatment: of insulating or insulated package substrates, or of interposers, or of redistribution layers
H10W 70/635
Vias, e.g. via plugs: through-vias

Family

Application09/713,834Parent of this continuation-in-part · filed 15 Nov 2000

Application09/878,815Parent of this division · filed 11 Jun 2001

US 6,960,824 B1Parent of this division

US 6,921,972 B1Parent of this continuation-in-part

Application09/878,815Parent of this continuation-in-part

US 7,247,516 B1This patent

From the US filing history. Foreign family members aren’t listed.

Method for fabricating a leadless chip carrier

Life of this patent

Method for fabricating a leadless chip carrier

Life of this patent

Abstract

Claims16