Buffer layer in flat panel display

#1. Field of the Invention

#This invention relates to preserving the electrical and optical properties of optically transparent and conductive films such as indium tin oxide (ITO), and more particularly, to providing a buffer or protective layer between aluminum and ITO for use in the fabrication of flat panel displays and the like.

#2. Description of the Related Art

#FIG. 1 is a schematic cross-sectional view of a flat panel display including a plurality of field emission devices.

#FIG. 2 is an isometric view of a baseplate of a flat panel display, showing an emitter set comprising a plurality of electron emission tips.

#FIG. 3 is a top view of the baseplate of flat panel display of FIG. 2, showing the addressable rows and columns.

#The preferred embodiments describe flat panel display devices, and more particularly, fabrication of the faceplate of an FED device using indium tin oxide and the like. It will be appreciated that although the preferred embodiments are described with respect to FED devices, the methods and apparatus taught herein are applicable to other flat panel display devices such as liquid crystal displays (LCDs), organic light emitting devices (OLEDs), plasma displays, vacuum fluorescent displays (VFDs), electroluminescent displays (ELDs), as well as solar cells. Other devices incorporating ITO and similar materials, such as other tin oxides, are also contemplated as being within the scope of this invention, as well as any device which employs an aluminum layer formed over an ITO or similar layer.

#FIG. 1 illustrates a portion of a flat panel display, including a plurality of field emission devices. Flat panel display 10 comprises a baseplate 12 and a faceplate 14. Baseplate 12 includes substrate 16, which is preferably formed from an insulative glass material. Column interconnects 18 are formed and patterned over substrate 16. The purpose and function of column interconnects 18 is disclosed in greater detail below. Furthermore, a resistor layer 20 may be disposed over column interconnects 18. Electron emission tips 22 are formed over substrate 16 at the sites from which electrons are to be emitted, and may be constructed in an etching process from a layer of amorphous silicon that has been deposited over substrate 16. Electron emission tips 22 are protrusions that may have one or many shapes, such as pyramids, cones, or other geometries that terminate at a fine point for the emission of electrons.

#An extraction grid 24, or gate, which is a conductive structure that supports a positive charge relative to the electron emission tips 22 during use, is separated from substrate 16 with a dielectric layer 26. Extraction grid 24 includes openings 28 through which electron emission tips 22 are exposed. Dielectric layer 26 electrically insulates extraction grid 24 from electron emission tips 22 and the associated column interconnects which electrically connect the emission tips with a voltage source 30.