US 7,245,638 B2 · Methods and systems for DSP-based receivers

Abstract

Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.

Claims63

Dependent claims

A method for receiving data signals, comprising the steps of:

(a) receiving a data signal having a symbol rate;
(b) generating N sampling signals having a first frequency that is lower than said symbol rate, said N sampling signals shifted in phase relative to one another;
(c) controlling N analog-to-digital converter (“ADC”) paths with said N sampling signals to sample said data signal at said phases;
(d) individually adjusting one or more parameters for each of said N ADC paths, including individually adjusting said N sampling signals to reduce phase errors between said received data signal and each of said N sampling signals in said N ADC paths;
and
(e) generating a digital signal representative of said received data signal from samples received from said N ADC paths.

3 more elements

A receiver, comprising:

a receiver input;
an analog-to-digital converter (“ADC”) array of N ADC paths, wherein N is an integer greater than 1, each said ADC path including an ADC path input coupled to said receiver input;
an M-path DSP coupled to said ADC array, wherein M=kN and k is an integer or a number in the form of 1/s, where s is an integer;
said M-path DSP having a timing recovery module, wherein said timing recovery module recovers N sampling clocks from a data signal received at said receiver input, said data signal having a baud frequency, said N sampling clocks having a first frequency that is N times lower than said baud frequency, said N sampling clocks being shifted in phase relative to one another, whereby said timing recovery module provides said N sampling clocks to said N ADC paths, whereby said N sampling clocks control said N ADC paths to sample said received signal at said phases;
and
means for individually adjusting one or more parameters for each of said N ADC paths, including means for adjusting each of said N sampling signals to reduce sampling phase errors in said N ADC paths.

3 more elements

Dependencies are inferred from the claim text.

Methods and systems for DSP-based receivers

Life of this patent

Methods and systems for DSP-based receivers

Life of this patent

Abstract

Claims63