Incremental checkpointing in a multi-threaded architecture
AssigneeIntel Corporation
InventorsShubhendu S. Mukherjee, Steven K. Reinhardt, Joel S. Emer
Life of this patent
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Abstract
A processor executes corresponding instruction threads as a leading thread and a trailing thread. For a selected instruction, processor state corresponding to the execution of the instruction is saved in a history buffer. This is performed before writing a result from the selected instruction to a destination register. The result from executing the selected instruction in the leading thread is compared to the result from executing the selected instruction in the trailing thread. If the comparison indicates a fault, then restoring the processor state corresponding to a previous instruction. Data from the history buffer is used to perform the restoration.
Claims29
A method comprising:
- executing corresponding instruction threads as a leading thread and a trailing thread;
- saving a processor state corresponding to execution of a selected instruction in a history buffer in connection with retiring the selected instruction and before committing a result from the selected instruction to a destination register;
- after retiring the selected instruction and committing the result from the selected instruction to the destination register, comparing the result from the selected instruction executed in the leading thread to the result from the selected instruction executed in the trailing thread;
- and
- restoring the processor state corresponding to a previous instruction using data from the history buffer if the comparison indicates a fault.
An apparatus comprising:
- means for executing corresponding threads as a leading thread and a trailing thread;
- means for saving a processor state corresponding to execution of a selected instruction in connection with retiring the selected instruction and before committing a result from the selected instruction to a destination register;
- means for, after retiring the selected instruction and committing the result from the selected instruction to the destination register, comparing the result from the selected instruction executed in the leading thread to the result from the selected instruction executed in the trailing thread;
- and
- means for restoring the processor state corresponding to a previous instruction if the comparison indicates a fault.
An apparatus comprising:
- leading thread execution circuitry to execute a leading thread of instructions;
- trailing thread execution circuitry to execute a trailing thread of instructions;
- and
- a history buffer coupled with the leading thread execution circuitry and the trailing thread execution circuitry to store information related to execution of a selected instruction from the leading thread of instructions, wherein the information related to execution of the selected instruction is stored in connection with retiring the selected instruction and before committing a result of the instruction to a destination register, wherein execution fault detection is performed after the selected instruction has been retired and the result of the instruction has been committed to the destination resister, and wherein the information stored in the history buffer is used to restore an architectural state corresponding to a checkpoint if an execution fault is detected.
A system comprising:
- leading thread execution circuitry to execute a leading thread of instructions;
- trailing thread execution circuitry to execute a trailing thread of instructions;
- an input/output controller coupled with the leading thread execution circuitry;
- and
- a history buffer coupled with the leading thread execution circuitry and the trailing thread execution circuitry to store information related to execution of a selected instruction from the leading thread of instructions, wherein the information related to execution of the selected instruction is stored in connection with retiring the selected instruction and before committing a result of the instruction to a destination register, wherein execution fault detection is performed after the selected instruction has been retired and the result of the instruction has been committed to the destination resister, and wherein the information stored in the history buffer is used to restore an architectural state corresponding to a checkpoint if an execution fault is detected.
Dependencies are inferred from the claim text.