Semiconductor device with signal line having decreased characteristic impedance
AssigneeOki Electric Industry Co., Ltd.
InventorNoritaka Anzai
Life of this patent
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Abstract
A semiconductor device includes a semiconductor chip, electrodes pads, an insulating layer, first and second conductive patterns and external terminals. The electrode pads are formed on a first area of a main surface of the semiconductor chip. The insulating layer is formed on a second area of the semiconductor chip so as to expose the electrode pads. The first conductive pattern provides a ground potential and is formed on the insulating layer. The second conductive pattern transfers a signal. The second conductive pattern is formed on the insulating layer and located to partially surround the first conductive pattern. The external terminals are formed on the first and second patterns at the second area.
Claims13
A semiconductor device, comprising:
- a semiconductor chip having a main surface, wherein the main surface has a first area, and a second area located outside and adjacently to the first area;
- first, second and third electrode pads formed on the main surface in the second area, wherein the first, second and third electrode pads are aligned with each other and wherein the second electrode pad is located between the first and third electrode pads;
- an insulating layer formed on the main surface in the first and second areas, wherein the first, second and third electrode pads are exposed from the insulating layer;
- a first exterior terminal formed above a top surface of the insulating layer in the first area;
- a second exterior terminal formed above the top surface of the insulating layer in the first area;
- a first conductive pattern extending on the top surface of the insulating layer, the first conductive pattern electrically connected to the first and third electrode pads, and electrically connected to the first exterior terminal between the first and third electrode pads;
- and
- a second conductive pattern extending on the top surface of the insulating layer, the second conductive pattern electrically connected to the second electrode pad and the second exterior terminal,
- wherein the first exterior terminal is located nearer to a center side of the main surface than the second exterior terminal, and wherein the first conductive pattern is positioned along lateral sides of the first exterior terminal to partially surround the first exterior terminal.
A semiconductor device, comprising:
- a semiconductor chip having a main surface, wherein the main surface has a first area, and a second area located outside and adjacently to the first area;
- first, second and third electrode pads formed on the main surface in the second area, wherein the first, second and third electrode pads are aligned with each other and wherein the second electrode pad is located between the first and third electrode pads;
- an insulating layer formed on the main surface in the first and second areas, wherein the first, second and third electrode pads are exposed from the insulating layer;
- a first exterior terminal formed above a top surface of the insulating layer in the first area;
- a second exterior terminal formed above the top surface of the insulating layer in the first area;
- a first conductive pattern extending on the top surface of the insulating layer, the first conductive pattern electrically connected to the first and third electrode pads, and electrically connected to the first exterior terminal between the first and third electrode pads;
- and
- a second conductive pattern extending on the top surface of the insulating layer, the second conductive pattern electrically connected to the second electrode pad and the second exterior terminal,
- wherein a width of the first conductive pattern is wider than a width of the second conductive pattern, and wherein the first conductive pattern is positioned along lateral sides of the first exterior terminal to partially surround the first exterior terminal.
Dependencies are inferred from the claim text.