US 7,236,557 B1 · Counter-based clock multiplier circuits and methods

Abstract

Clock multiplier circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and the counted value is stored. The stored value is then divided and the divided values are combined to provide counter stop values representing the numbers of counts in various fractions of the input clock period. A second counter counts from an initial value starting from a first edge of the input clock, and the count is compared in turn to the each of the counter stop values. When the value in the second counter matches one of the counter stop values, a pulse is generated on the output clock signal. Thus, the second counter generates a series of pulses at predetermined times in the input clock period.

Claims20

Dependent claims

A system comprising a clock multiplier circuit, the clock multiplier circuit comprising:

a counter circuit having a clock input terminal, a clock output terminal, and a plurality of count output terminals;
a register having a plurality of data input terminals coupled to the count output terminals of the counter circuit, a clock input terminal coupled to the clock output terminal of the counter circuit, and a plurality of output terminals;
a stop value generator circuit having a plurality of data input terminals coupled to the output terminals of the register, a clock input terminal coupled to the clock output terminal of the counter circuit, and a plurality of output terminals;
and
an output clock generator having a plurality of input terminals coupled to the output terminals of the stop value generator circuit, a clock input terminal coupled to the clock input terminal of the counter circuit, and a clock output terminal.

2 more elements

Dependencies are inferred from the claim text.

Counter-based clock multiplier circuits and methods

Life of this patent

Counter-based clock multiplier circuits and methods

Life of this patent

Abstract

Claims20