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US 7,235,822 B2Granted
Transistor with silicon and carbon layer in the channel region
AssigneeInfineon Technologies AG
InventorHong-Jyh Li
Life of this patent
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Abstract
A transistor and method of manufacturing thereof having stressed material layers formed in the channel to increase the speed and improve performance of the transistor. A layer of silicon and carbon is epitaxially grown in the channel region. A thin semiconductor material may be formed over the layer of silicon and carbon, and a stressed semiconductor layer may be epitaxially grown prior to forming the layer of silicon and carbon.
Claims11
A transistor, comprising:
- a workpiece;
- a stressed layer selected from the group of semiconductor material consisting of silicon and silicon with carbon disposed over the workpiece and wherein the amount of carbon in said silicon and carbon layer is less than a first amount;
- a first layer of silicon and carbon disposed directly on the stressed layer wherein the amount of carbon in said first layer is said first amount;
- a gate dielectric disposed over said first layer of silicon and carbon;
- a gate disposed over the gate dielectric;
- and
- a source region and a drain region formed in the layer of silicon and carbon and stressed semiconductor layer.
4 more elements
Dependencies are inferred from the claim text.