US 7,233,522 B2Granted

NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

AssigneeSanDisk 3D LLC

InventorsEn-Hsing Chen, Andrew J. Walker, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca G. Fasoli

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Abstract

An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

Claims44

Dependent claims

A method of operating an integrated circuit having a memory array including at least one plane of memory cells, said memory cells comprising switch devices having a charge storage dielectric and which cells are arranged in a plurality of series-connected NAND strings, said method comprising the steps of:

biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage;
and then
capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell;
wherein the biasing step comprises:
(a) conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string;
(b) coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string;
and
(c) turning on the half-selected memory cell and any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string;
and then
(d) decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage;
wherein the method further comprises:
(e) coupling a first end of a selected NAND string of the selected memory block through a first group of at least one series selection device, to a respective first array line associated with the selected NAND string, said respective first array line conveying a bit line programming voltage;
(f) coupling the bit line programming voltage to a channel region of a selected memory cell in the selected NAND string, said selected memory cell also associated with the selected word line;
(g) turning off at least one device of a second group of at least one series selection device at a second end of the unselected NAND string opposite the first end, said second group of at least one series selection device for coupling said unselected NAND string to a respective second array line associated with the unselected NAND string;
and
(h) turning off at least one device of a second group of at least one series selection device at a second end of the selected NAND string opposite the first end, said second group of at least one series selection device for coupling said selected NAND string to a respective second array line associated with the selected NAND string.

13 more elements

A method of operating an integrated circuit having a memory array including at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said method comprising the steps of:

biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage;
and then
capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell;
wherein the biasing step comprises:
(a) conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string;
(b) coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string;
and
(c) turning on the half-selected memory cell and any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string;
and then
(d) decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage;
wherein the method further comprises:
(e) coupling a first end of a selected NAND string of the selected memory block through a first group of at least one series selection device, to a respective first array line associated with the selected NAND string, said respective first array line conveying a bit line programming voltage;
(f) coupling the bit line programming voltage to a channel region of a selected memory cell in the selected NAND string, said selected memory cell also associated with the selected word line;
(g) turning off at least one device of a second group of at least one series selection device at a second end of the unselected NAND string opposite the first end, said second group of at least one series selection device for coupling said unselected NAND string to a respective second array line associated with the unselected NAND string;
and
(h) turning off at least one device of a second group of at least one series selection device at a second end of the selected NAND string opposite the first end, said second group of at least one series selection device for coupling said selected NAND string to a respective second array line associated with the selected NAND string.

13 more elements

An integrated circuit comprising:

a memory array having at least one plane of memory cells, said memory cells comprising switch devices having a charge storage dielectric and which cells are arranged in a plurality of series-connected NAND strings;
and
means for biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage;
and
means for capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell;
wherein the means for biasing comprises:
means for conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string;
means for coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string;
and
means for turning on the half-selected memory cell and any intevening memory cells between the half-selected memory cell and the first end of the unselected NAND string;
and
means for decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage;
said integrated circuit further comprising:
means for coupling a first end of a selected NAND string of the selected memory block through a first group of at least one series selection device, to a respective first array line associated with the selected NAND string, said respective first array line conveying a bit line programming voltage;
means for coupling the bit line programming voltage to a channel region of a selected memory cell in the selected NAND string, said selected memory cell also associated with the selected word line;
means for turning off at least one device of a second group of at least one series selection device at a second end of the unselected NAND string opposite the first end, said second group of at least one series selection device for coupling said unselected NAND string to a respective second array line associated with the unselected NAND string;
and
means for turning off at least one device of a second group of at least one series selection device at a second end of the selected NAND string opposite the first end, said second group of at least one series selection device for coupling said selected NAND string to a respective second array line associated with the selected NAND string.

15 more elements

An integrated circuit comprising:

a memory array having at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings;
and
means for biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage;
and
means for capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell;
wherein the means for biasing comprises:
means for conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string;
means for coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string;
and
means for turning on the half-selected memory cell and any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string;
and
means for decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage;
said integrated circuit further comprising:
means for coupling a first end of a selected NAND string of the selected memory block through a first group of at least one series selection device, to a respective first array line associated with the selected NAND string, said respective first array line conveying a bit line programming voltage;
means for coupling the bit line programming voltage to a channel region of a selected memory cell in the selected NAND string, said selected memory cell also associated with the selected word line;
means for turning off at least one device of a second group of at least one series selection device at a second end of the unselected NAND string opposite the first end, said second group of at least one series selection device for coupling said unselected NAND string to a respective second array line associated with the unselected NAND string;
and
means for turning off at least one device of a second group of at least one series selection device at a second end of the selected NAND string opposite the first end, said second group of at least one series selection device for coupling said selected NAND string to a respective second array line associated with the selected NAND string.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/729,831Filed 5 Dec 2003 · continuation in part
Priority: 31 Dec 2002
Published: US 2004/0125629 A129 Jul 2004
Granted: 19 Jun 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11C 16/3418
Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention: disturbance prevention or evaluation;…
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/3427
Disturbance prevention or evaluation; Refreshing of disturbed memory data: circuits or methods to prevent or reduce disturbance of the state of a…
H10B 43/30
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region

Family

Application10/335,078Parent of this continuation-in-part · filed 31 Dec 2002
US 2004/0145024 A1Pre-grant publication · published 29 Jul 2004
US 2004/0125629 A1Published application
US 7,505,321 B2Related patent
US 7,233,522 B2This patent

From the US filing history. Foreign family members aren’t listed.