US 7,233,024 B2 · Three-dimensional memory device incorporating segmented bit line memory array

Abstract

A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.

Claims37

Dependent claims

An integrated circuit comprising:

a three-dimensional memory array having a respective plurality of word lines on each of at least one layer of the memory array, having a respective plurality of bit line segments on each of at least two layers of the memory array, defining a memory layer for each vertically adjacent word line layer and segmented bit line layer;
and
a respective plurality of global bit lines on each of at least a first global bit line layer;
a respective plurality of memory segments on each of said memory layers, each memory segment comprising
a respective plurality of memory cells coupled to a respective bit line segment;
and
a respective segment switch device for coupling the respective bit line segment to an associated global bit line by way of a vertical connection which is shared by at least one memory segment on each of at least two memory layers.

4 more elements

Dependencies are inferred from the claim text.

Three-dimensional memory device incorporating segmented bit line memory array

Life of this patent

Three-dimensional memory device incorporating segmented bit line memory array

Life of this patent

Abstract

Claims37