Method and circuit for cascaded pulse width modulation

A method of balancing the voltage of DC links in a cascaded multi-level converter (CMC) semiconductor circuit, comprising the steps of:

• (a) providing a plurality of H-bridge converters in the CMC circuit;
• (b) utilizing a three phase command multilevel duty cycle value from the main controller to determine a normalized duty cycle value, a ceiling duty cycle value and a floor duty cycle value;
• (c) utilizing the normalized duty cycle value and an output current of the CMC to determine the direction and polarity of the normalized duty cycle value and a capacitor current, and utilizing the capacitor current to determine a plurality of output capacitor voltages;
• (d) sorting the capacitor voltages to obtain a register containing a plurality of indices representing sorted capacitor voltages;
• (e) inputting the multi-level duty cycle voltage, the direction and polarity of the duty cycle output voltage and the sorted capacitor voltages into an index generator;
• (f) calculating a ceiling index pointer and a floor index pointer wherein the ceiling index pointer corresponds to an input ceiling duty cycle representing a number of the plurality of H-bridge converters required to generate a positive output voltage, and the floor index pointer corresponds to an input floor duty cycle representing a number of the plurality of H-bridge converters required to generate a negative output voltage;
• (g) determining a voltage summation result and direction from the ceiling index pointer and a floor index pointer;
• (h) utilizing the voltage summation result and direction from the ceiling index pointer and a floor index pointer to create a combined switching table for the H-bridge converters;
• and
• (i) utilizing a pulse width modulator to balance the voltage of the DC links and thereby eliminate DC-capacitor voltage imbalance.

A circuit for balancing the voltage of DC links in a cascaded multi-level converter (CMC), comprising:

• (a) a plurality of H-bridge converters;
• (b) a main controller for utilizing a three phase duty cycle value to determine a normalized duty cycle value, a ceiling duty cycle value and a floor duty cycle value;
• (c) a direction and duty cycle check circuit utilizing the normalized duty cycle value and an output current of the CMC to determine the direction and polarity of a capacitor current, and utilizing the capacitor current to determine a plurality of output capacitor voltages;
• (d) a sorting network circuit for sorting the capacitor voltages to obtain a register representing sorted capacitor voltages;
• (e) an index generator for receiving the multi-level duty cycle voltage, the polarity of the duty cycle output voltage and the sorted capacitor voltages and calculating a ceiling index pointer and a floor index pointer wherein the ceiling index pointer corresponds to an input ceiling duty cycle representing a number of the plurality of H-bridge converters required to generate a positive output voltage, and the floor index pointer corresponds to an input floor duty cycle representing a number of the plurality of H-bridge converters required to generate a negative output voltage, determining therefrom a voltage summation result and direction from the ceiling index pointer and a floor index pointer, and utilizing the voltage summation result, direction from the ceiling index pointer and a floor index pointer to create a combined switching table for the H-bridge converters;
• and
• (f) utilizing a pulse width modulator to balance the voltage of the DC links and thereby eliminate DC-capacitor voltage imbalance.