Semiconductor integrated circuit device and its manufacture using automatic layout
AssigneeYamaha Corporation
InventorYukichi Ono
Life of this patent
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Abstract
A semiconductor integrated circuit device has: a semiconductor substrate defining a plurality of rows, each row including areas for a sequence of cells; a plurality of active regions disposed in each of the rows constituting semiconductor elements of associated cells; and a wiring region of stripe shape elongated along a direction of row, defined on the semiconductor substrate outside of the active regions in each row, and including wirings belonging to the associated cells, each wiring region having height in a direction crossing the row direction, the wiring region having locally different height.
Claims18
A method of laying out a semiconductor integrated circuit device comprising:
- (a) decomposing circuit data into cells, and reading cell data including configuration data and interconnection data;
- (b) grouping cells on a semiconductor substrate into a plurality of rows, each of said rows including a plurality of cells aligned along a direction of a row, each cell including active regions, shape-fixed wiring regions disposed over the active regions, and shape-variable wiring regions disposed outside the active regions and having height along a direction crossing a direction of said row;
- (c) designing a layout of wirings in said shape-fixed wiring region;
- (d) designing a layout of wirings in said shape-variable wiring region;
- (e) checking possible variations of wirings in said shape-variable wiring region, for a pair of adjacent rows of cells grouped in said step (b), which will produce shape-variable wiring regions of locally varied height capable of a mutually fitting configuration, and which can reduce the distance between said pair of adjacent rows;
- and
- (f) if there is a variation which can reduce the distance between said pair of adjacent rows, redesigning the layout of wirings in the shape-variable wiring region to realize mutually fitting shape-variable wiring regions.
A method of designing a layout of a semiconductor integrated circuit device comprising:
- (a) decomposing circuit data into cells, and reading cell data including configuration data and interconnection data;
- (b) locating cells on a virtual semiconductor substrate into a plurality of rows, each of said rows including a plurality of cells aligned along a direction of a row, each cell including active regions, shape-fixed wiring regions disposed over the active regions, and shape-variable wiring regions disposed outside the active regions and having height along a direction crossing the direction of the row;
- (c) designing a layout of wirings in said shape-fixed wiring region;
- (d) designing a layout of wirings in said shape-variable wiring region;
- (e) checking possible variations of wirings in said shape-variable wiring region, for a pair of adjacent rows of cells located in step (b), which will produce shape-variable wiring regions of locally varied height capable of mutually fitting configuration, which can reduce the distance between said pair of adjacent rows;
- and
- (f) if there is a variation which can reduce the distance between said pair of adjacent rows, redesigning the layout of wirings in the shape-variable wiring region to realize mutually fitting shape-variable wiring regions.
A computer-readable medium having encoded thereon a computer-readable program code which when executed causes a computer to:
- (a) decompose circuit data into cells, and read cell data including configuration data and interconnection data;
- (b) group cells on a virtual semiconductor substrate into a plurality of rows, each of said rows including a plurality of cells aligned along a direction of a row, each cell including active regions, shape-fixed wiring regions disposed over the active regions, and shape-variable wiring regions disposed outside the active regions and having height along a direction crossing the direction of the row;
- (c) design a layout of wirings in said shape-fixed wiring region;
- (d) design a layout of wirings in said shape-variable wiring region;
- (e) check possible variations of wirings in said shape-variable wiring region, for a pair of adjacent rows of cells grouped in step (b), which will produce shape-variable wiring regions of locally varied height capable of mutually fitting configuration, which can reduce the distance between said pair of adjacent
- (f) if there is a variation which can reduce the distance between said pair of adjacent rows, redesign the layout of wirings in the shape-variable wiring regions.
Dependencies are inferred from the claim text.