Memory system for portable telephone
AssigneeRenesas Technology Corp.
InventorsTakayuki Shinohara, Masatoshi Kimura
Life of this patent
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Abstract
A memory system is constituted of a file storage flash memory storing a control program required for a control portion and a large amount of data, and a random access memory storing a program used by the control portion and functioning as a buffer memory for received data. Thus, a memory system for a portable telephone capable of storing a large amount of received data at high-speed and allowing reading of the stored data at high-speed is provided.
Claims19
A memory system for a portable telephone including a signal transmission/reception portion for transmitting and receiving a signal and a control portion for controlling at least a signal transmission and reception operation of said transmission/reception portion, comprising:
- a random access memory providing a working area for said control portion;
- and
- a flash memory including a memory array storing a program for said control portion and at least transmission and reception data in a non-volatile manner under a control of said control portion, said memory array being divided into a plurality of storage units, and a register, provided commonly to the respective storage units, having information in a storage unit of said plurality of storage units transmitted thereinto for temporal storage of the transmitted information and allowing serial readout of the transmitted and stored information.
A memory system for a portable telephone including a signal transmission/reception portion transmitting and receiving a signal, and a control portion controlling at least a signal transmission and reception operation of said signal transmission/reception portion, comprising:
- a random access memory providing a working area for said control portion;
- and
- a flash memory including a memory array storing a program for said control portion and at least transmission and reception data in a non-volatile manner under a control of said control portion, said memory array being divided into a plurality of storage units, a plurality of pieces of information in one unit of the storage units selected in accordance with an address signal at a time, being allowed to be serially read out in synchronization with a clock signal without further address application.
Dependencies are inferred from the claim text.