Error detection and correction method
OwnerThomas F. Lehmaninventor
Life of this patent
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Abstract
A method for error detection and correction of a memory, preferably a flash memory that utilizes existing on-chip circuitry to implement the error correction and detection process is disclosed. The present invention is able to detect and correct single bit errors, while detecting multi-bit errors in data storage circuitry. The method is embodied in a software routine, which when actively operative, uses a multiply accumulate circuit (MAC) and on chip cache located on memory controller circuitry for error correction of errors incurred through the storage of data to a storage device.
Claims40
A method comprising:
- receiving a series of bit data groupings, Dn;
- generating a first value S0, determined by a relationship
- (
- S
- 0
- =
- ∑
- i
- =
- 0
- n
- -
- 1
-
- X
- 1
- *
- D
- i
- )
- ,
- wherein n comprises a total number of bit data groupings, Di comprises each bit data grouping of the bit data groupings Dn, and Xi comprises a weighted coefficient;
- and
- storing the bit data groupings, Dn, and the first value, S0.
A device comprising:
- a circuit configured to receive a series of bit data groupings, Dn;
- a multiply accumulator configured to generate a first value S0, determined by a relationship
- (
- S
- 0
- =
- ∑
- i
- =
- 0
- n
- -
- 1
-
- X
- i
- *
- D
- i
- )
- ,
- wherein n comprises a total number of bit data groupings, Di comprises each bit data grouping of the bit data groupings Dn, and Xi comprises a weighted coefficient;
- and
- a storage circuit configured to store the bit data groupings, Dn, and the first value, S0.
A method comprising:
- receiving a series of bit data groupings, Dn;
- generating a first value S0, determined by a relationship
- (
- S
- 0
- =
- ∑
- i
- =
- 0
- n
- -
- 1
-
- C
- i
- *
- Wt
-
- (
- B
- i
- )
- +
- G
-
- (
- B
- i
- )
- )
- ,
- wherein “n” comprises a total number of bit data groupings, “i” comprises an integer index value increasing from 0→n−1, Wt(Bi) represents the weight of the data being acted upon, G(Bi) represents the sum of the bit positions, and “Ci” comprises an offset value;
- and
- storing the bit data groupings, Dn, and the first value, S0.
A device comprising:
- a circuit configured to receive a series of bit data groupings, Dn;
- a multiply accumulator configured to generate a first value S0, determined by a relationship
- (
- S
- 0
- =
- ∑
- i
- =
- 0
- n
- -
- 1
-
- C
- i
- *
- Wt
-
- (
- B
- i
- )
- +
- G
-
- (
- B
- i
- )
- )
- ,
- wherein n comprises a total number of bit data groupings, “i” comprises an integer index value increasing from 0→n−1, Wt(Bi) represents the weight of the data being acted upon, G(Bi) represents the sum of the bit positions, and “Ci” comprises an offset value;
- and
- a storage circuit configured to store the bit data groupings, Dn, and the first value, S0.
Dependencies are inferred from the claim text.