Mask-making member and its production method, mask and its making method, exposure process, and fabrication method of semiconductor device

A method of producing a mask-making member, said member has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed, said supporting region being provided for holding said plurality of pattern formation regions while separating said plurality of pattern formation regions from each other, said supporting region having first alignment marks used at the time of alignment with a mask made from said mask-making member for forming said mask circuit patterns thereon, second alignment marks being used at a time of alignment with a substrate to be exposed for forming circuit patterns thereon, said method comprising the step of:

• forming all of said first alignment marks and said second alignment marks on said mask-making member at one time, said first alignment marks being formed in such a manner that one or more of said first alignment marks are located in a portion of said supporting region around each of said plurality of pattern formation regions and said second alignment marks being formed in such a manner as to be all located in a portion of said supporting region outside an area formed by said plurality of said pattern formation regions, and the alignment with said mask-making member for forming said first alignment marks and said second alignment marks thereon at one time is performed by using a scanner type exposure system with a projected magnification of a 1:1 ratio or a low reduction ratio.

A method of producing a mask-making member, said member has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed, said supporting region being provided for holding said plurality of pattern formation regions while separating said plurality of pattern formation regions from each other, said supporting region having first alignment marks used at the time of alignment with a mask made from said mask-making member for forming said mask circuit patterns thereon, second alignment marks being used at a time of alignment with a substrate to be exposed for forming circuit patterns thereon, said method comprising the step of:

• forming all of said first alignment marks and said second alignment marks on said mask-making member at one time, said first alignment marks being formed in such a manner that one or more of said first alignment marks are located in a portion of said supporting region around each of said plurality of pattern formation regions and said second alignment marks being formed in such a manner as to be all located in a portion of said supporting region outside an area formed by said plurality of said pattern formation regions, and the alignment with said mask-making member for forming said first alignment marks and said second alignment marks thereon at one time is performed by using a contact type full exposure system.

A method of producing a mask-making member, said member has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed, said supporting region being provided for holding said plurality of pattern formation regions while separating said plurality of pattern formation regions from each other, said supporting region having first alignment marks used at the time of alignment with a mask made from said mask-making member for forming said mask circuit patterns thereon, second alignment marks being used at a time of alignment with a substrate to be exposed for forming circuit patterns thereon, said method comprising the step of:

• forming all of said first alignment marks and said second alignment marks on said mask-making member at one time, said first alignment marks being formed in such a manner that one or more of said first alignment marks are located in a portion of said supporting region around each of said plurality of pattern formation regions and said second alignment marks being formed in such a manner as to be all located in a portion of said supporting region outside an area formed by said plurality of said pattern formation regions, and the alignment with said mask-making member for forming said first alignment marks and said second alignment marks thereon at one time is performed by using a proximity type full exposure system.

A method of producing a mask-making member, said member has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed, said supporting region being provided for holding said plurality of pattern formation regions while separating said plurality of pattern formation regions from each other, said supporting region having first alignment marks used at the time of alignment with a mask made from said mask-making member for forming said mask circuit patterns thereon, second alignment marks being used at a time of alignment with a substrate to be exposed for forming circuit patterns thereon, said method comprising the step of:

• forming all of said first alignment marks and said second alignment marks on said mask-making member at one time, said first alignment marks being formed in such a manner that one or more of said first alignment marks are located in a portion of said supporting region around each of said plurality of pattern formation regions and said second alignment marks being formed in such a manner as to be all located in a portion of said supporting region outside an area formed by said plurality of said pattern formation regions, and the alignment with said mask-making member for forming said first alignment marks and said second alignment marks thereon at one time is performed by using a mirror-projections type full exposure system.

A method of making a mask, which mask has a plurality of pattern formation regions in which mask circuit patterns are formed, and a supporting region in which any mask circuit pattern is not formed, said supporting region being provided for holding said plurality of pattern formation regions while separating said plurality of pattern formation regions from each other, wherein said supporting region has first alignment marks used at a time of alignment with said mask for forming said mask circuit patterns thereon, second alignment marks used at a time of alignment with a substrate to be exposed for forming circuit patterns thereon, said method comprising the step of:

• forming all of said first alignment marks and said second alignment marks on said mask at one time;
• wherein said plurality of pattern formation regions are exposed to charged particle beams by using said first alignment marks for forming said mask circuit patterns on said plurality of pattern formation regions;
• and
• wherein said alignment with said plurality of pattern formation regions to the charged particle beams is performed by using a charged particle beam exposure system configured such that the charged particle beam has a size of 10 μm or less and a maximum deflection width of the charged particle beam in a state that a stage on which an electron-optical system is mounted is not moved is larger than a total of a width of each of said plurality of pattern formation regions and a width of a portion of said supporting region between two of said plurality of pattern formation regions.

A method of making a mask, which mask has a plurality of pattern formation regions in which mask circuit patterns are formed, and a supporting region in which any mask circuit pattern is not formed, said supporting region being provided for holding said plurality of pattern formation regions while separating said plurality of pattern formation regions from each other, wherein said supporting region has first alignment marks used at a time of alignment with said mask for forming said mask circuit patterns thereon, second alignment marks used at a time of alignment with a substrate to be exposed for forming circuit patterns thereon, said method comprising the step of:

• forming all of said first alignment marks and said second alignment marks on said mask at one time;
• wherein said mask is a stencil mask;
• and
• wherein said first alignment marks and said second alignment marks are formed on a mask board by selectively removing said mask board to form holes or grooves in said mask board and burying said holes or grooves with a metal whose atoms have atomic weights heavier than those of atoms of said mask board.

A method of making a mask, which mask has a plurality of pattern formation regions in which mask circuit patterns are formed, and a supporting region in which any mask circuit pattern is not formed, said supporting region being provided for holding said plurality of pattern formation regions while separating said plurality of pattern formation regions from each other, said supporting region having first alignment marks used at the time of alignment with said mask for forming said mask circuit patterns thereon, second alignment marks being used at a time of alignment with a substrate to be exposed for forming circuit patterns thereon, said second alignment marks being used for alignment with a substrate to be exposed by a charged particle beam reduction-and-division transfer exposure system by using said second alignment marks, said method comprising the steps of:

• performing alignment with a substrate to be exposed by said charged particle beam reduction-and-division transfer exposure system by using a test mask having a positional deviation measurement pattern, to dividedly transfer said positional deviation measurement pattern on said substrate at a specific reduction ratio;
• obtaining a positional deviation amount of said charged particle beam reduction-and-division transfer exposure system upon exposure and a correction amount for correcting the positional deviation amount by using the positional deviation measurement pattern which has been dividedly transferred on said substrate at the specific reduction ratio;
• and
• performing alignment with said mask for forming said mask circuit patterns while correcting said mask circuit patterns by the correction amount for the positional deviation so as to correct the positional deviation amount of said charged particle beam reduction-and-division transfer exposure system, to thereby correct said mask.

An exposure process comprising the steps of:

• producing a mask having a plurality of pattern formation regions in which mask circuit patterns are formed, and a supporting region in which any mask circuit pattern is not formed, said supporting region being provided for holding said plurality of pattern formation regions while separating said plurality of pattern formation regions from each other, said supporting region having first alignment marks used at the time of alignment with said mask for forming said mask circuit patterns thereon, second alignment marks being used at a time of alignment with a substrate to be exposed for forming circuit patterns thereon;
• and performing alignment with a substrate to be exposed by a charged particle beam reduction-and-division transfer exposure system using said second alignment marks formed on said mask
• wherein,
• a substrate to be exposed is exposed by said charged particle beam reduction-and-division transfer exposure system by using a test mask having a positional deviation measurement pattern, to dividedly transfer said positional deviation measurement pattern on said substrate at a specific reduction ratio;
• a positional deviation amount of said charged particle beam reduction-and-division transfer exposure system upon exposure and a correction amount for correcting the positional deviation amount are obtained by using the positional deviation measurement pattern which has been dividedly transferred on said substrate at the specific reduction ratio;
• alignment with said mask for forming said mask circuit patterns thereon while correcting said mask circuit patterns by the correction amount for the positional deviation is performed so as to correct the positional deviation amount of said charged particle beam reduction-and-deviation transfer exposure system, to thereby correct said mask;
• and
• alignment with a substrate to be exposed by said charged particle beam reduction-and-division transfer exposure system is performed by using said corrected mask.