# US 7,220,287 B1 · Method for tuning an embedded capacitor in a multilayer circuit board

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- Number: US 7,220,287 B1
- Document ID: US7220287B1
- Status: Granted
- Kind: B1
- Application number: 10/653,289
- Filed: 2003-09-03
- Granted: 2007-05-22
- Earliest claimed: 2003-09-03
- Assignees: Nortel Networks Limited
- Inventors: Aneta Wyrzykowska; Herman Kwong
- Web page: https://patentgrep.com/patent/US7220287B1

## CPC

- H10W 70/685: comprising multiple insulating layers
- H05K 1/162: {incorporating printed capacitors}
- H05K 1/113: {Via provided in pad; Pad over filled via}
- H05K 1/116: {Lands, clearance holes or other lay-out details concerning the surrounding of a via}
- H05K 3/0047: {Drilling of holes}
- H05K 3/429: {Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers}
- H05K 2201/0959: Plated through-holes or plated blind vias filled with insulating material
- H05K 2201/09627: Special connections between adjacent vias, not for grounding vias
- H05K 2203/0207: Partly drilling through substrate until a controlled depth, e.g. with end-point detection
- H05K 2203/0242: Cutting around hole, e.g. for disconnecting land or Plated Through-Hole [PTH] or for partly removing a PTH
- H05K 2203/171: Tuning, e.g. by trimming of printed components or high frequency circuits
- H05K 2203/173: Adding connections between adjacent pads or conductors, e.g. for modifying or repairing
- H05K 2203/175: Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/43: Electric condenser making
- Y10T 29/435: Solid dielectric type
- Y10T 29/49155: Manufacturing circuit on or in base
- Y10T 29/49156: with selective destruction of conductive paths
- Y10T 29/49165: by forming conductive walled aperture in base
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

Exemplary techniques for tuning the effective capacitance provided by an embedded capacitor are disclosed. The techniques may be realized by modifying one or more conductive features of one or more vias connected to the embedded capacitor to adjust the capacitance contributed by the one or more vias. One technique preferably includes altering the conductive surface area of a pad of one or more vias to which the embedded capacitor is electrically connected to increase or decrease the contributed capacitance. Another technique provides for bore drilling or tap drilling one or more vias connected to the embedded capacitor to increase the surface area of plated interior surfaces of the vias, thereby increasing their capacitive effect. An additional technique includes forming a number of vias having various capacitive effects and electrically connecting the embedded capacitor to one or more of these vias to increase the capacitance.

## Claims

### Claim 1

A method for tuning an effective capacitance of an embedded capacitor in a multilayer circuit board, the embedded capacitor having an embedded capacitor structure in the multilayer circuit board, the embedded capacitor structure being electrically connected to at least one electrically conductive via that electrically interconnects layers of the multilayer circuit board, the embedded capacitor structure having an associated embedded capacitor structure capacitance, the at least one electrically conductive via having a via capacitance, the effective capacitance comprising the embedded capacitor structure capacitance and the via capacitance, the method comprising the step of:
modifying at least one electrically conductive feature of the at least one electrically conductive via to change the via capacitance and the effective capacitance of the embedded capacitor without changing the embedded capacitor structure capacitance of the embedded capacitor.

### Claim 2 (depends on 1)

The method as in claim 1, wherein the at least one electrically conductive feature includes an electrically conductive surface area of a surface pad of the at least one electrically conductive via on an outer surface of the multilayer circuit board.

### Claim 3 (depends on 2)

The method as in claim 2, wherein the step of modifying the at least one electrically conductive feature includes reducing the electrically conductive surface area of the surface pad to reduce the via capacitance and the effective capacitance of the embedded capacitor without changing the embedded capacitor structure capacitance of the embedded capacitor.

### Claim 4 (depends on 2)

The method as in claim 2, wherein the step of modifying the at least one electrically conductive feature includes increasing the electrically conductive surface area of the surface pad to increase the via capacitance and the effective capacitance of the embedded capacitor without changing the embedded capacitor structure capacitance of the embedded capacitor.

### Claim 5 (depends on 4)

The method as in claim 4, wherein increasing the electrically conductive surface area of the surface pad includes increasing a diameter of the surface pad.

### Claim 6 (depends on 4)

The method as in claim 4, wherein increasing the electrically conductive surface area of the surface pad includes forming an electrically conductive plane on the outer surface of the multilayer circuit board, the electrically conductive plane being proximal to and electrically connected to the surface pad.

### Claim 7 (depends on 1)

The method as in claim 1, wherein the at least one electrically conductive feature includes an electrically conductive plating on an interior surface of the at least one electrically conductive via.

### Claim 8 (depends on 7)

The method as in claim 7, wherein the step of modifying the at least one electrically conductive feature includes counter drilling the at least one electrically conductive via to remove at least part of the electrically conductive plating from the interior surface of the at least one electrically conductive via to reduce the via capacitance and the effective capacitance of the embedded capacitor without changing the embedded capacitor structure capacitance of the embedded capacitor.

### Claim 9 (depends on 8)

The method as in claim 8, wherein the interior surface of the at least one electrically conductive via has a substantially conical shape.

### Claim 10 (depends on 7)

The method as in claim 7, wherein the step of modifying the at least one electrically conductive feature includes tap drilling the multilayer circuit board so that the at least one electrically conductive via has a substantially conical shape before the interior surface of the at least one electrically conductive via is plated with electrically conductive material.

### Claim 11 (depends on 1)

The method as in claim 1, wherein the at least one electrically conductive feature includes an electrically conductive trace connecting the embedded capacitor to the at least one electrically conductive via.

### Claim 12 (depends on 1)

The method as in claim 1, further comprising the step of:
electrically connecting the at least one electrically conductive via to at least one of one or more auxiliary vias formed in the multilayer circuit board to further change the via capacitance and the effective capacitance of the embedded capacitor without changing the embedded capacitor structure capacitance of the embedded capacitor.

### Claim 13 (depends on 12)

The method as in claim 12, wherein the step of electrically connecting the at least one electrically conductive via to at least one of the one or more auxiliary vias includes forming at least one conductive trace between a surface pad of the at least one electrically conductive via and a respective surface pad of each of the at least one of the one or more auxiliary vias.

### Claim 14 (depends on 12)

The method as in claim 12, further comprising the step of counter drilling at least one of the one or more auxiliary vias to remove at least part of electrically conductive plating from at least one interior surface of each of the at least one of the one or more auxiliary vias to reduce the via capacitance and the effective capacitance of the embedded capacitor without changing the embedded capacitor structure capacitance of the embedded capacitor.

### Claim 15 (depends on 1)

The method as in claim 1, wherein the multilayer circuit board is prefabricated.