Status indication detection and device and method
AssigneeTelefonaktiebolaget LM Ericsson (publ)
InventorHans-Ulrich Fleer
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Abstract
A status indication detection apparatus comprises an input storage stage, an intermediate storage stage and an output storage stage. Status indications are input into the input register of the input stage and are shifted to the intermediate and to the output stage. The input and intermediate storage stages operate with a first reference clock in a first clock domain whilst the output storage stage operates with a different second reference clock in the second clock domain. In accordance with the invention a reading out of the intermediate register of the intermediate stage is only possible during the generation of a hold signal which keeps a current status indication in the intermediate storage stage and blocks a transfer of a new status indication from the input stage.
Claims29
A method for detecting status indications, comprising the steps of:
- a1) raw status indications are read into an input storage stage of a first reference clock domain such that the read status indications are available in said input storage stage synchronized to a first reference clock of said first reference clock domain;
- a2) said read status indications are input into an output storage stage of a second reference clock domain, such that the status indications are available in said output storage stage synchronized to a second reference clock of said second reference clock domain, said second reference clock of said second reference clock domain having a different phase and/or frequency to said first reference clock;
- b) said status indications in said input storage stage are shifted to an intermediate storage stage of said first reference clock domain synchronized to said first reference clock;
- and
- c) in response to a read request signal being input into said output storage stage:
- c1) a hold signal is applied to said intermediate storage stage for holding a current status indication in said intermediate storage stage and blocking a shifting of a new status indication from said input to said intermediate storage stage;
- and
- c2) during said hold signal a read out signal is applied to said output storage stage for reading the current status indication in said intermediate storage stage into said output storage stage synchronized to said second reference clock.
A method according to claim, characterized in that wherein
- in said step c1), in a synchronisation stage of said intermediate storage stage said read lock pulse (RDLCK) is synchronized to said first reference clock and said hold signal having a pulse length of at least the duration of the synchronized read lock pulse is derived from said synchronized read lock pulse.
A status indication detection apparatus for detecting raw status indications, comprising:
- a1) an input storage stage of a first reference clock domain for reading said raw status indications such that the read status indications are available in said input storage stage synchronized to a first reference clock of said first reference clock domain;
- and
- a2) an output storage stage of a second reference clock domain into which said read status indications are input such that the status indications are available in said output storage stage synchronized to a second reference clock of said second reference clock domain, said second reference clock of said second reference clock domain having a different phase and/or frequency to said first reference clock;
- b) an intermediate storage stage of said first reference clock domain is provided between the input storage stage and the output storage stage, wherein said status indications in said input storage stage are shifted to an intermediate register of said intermediate storage stage synchronized to said first reference clock;
- c1) wherein said output storage stage further comprises a control pulse generator for generating a read out signal to be applied to an output register (ORM) of said output storage stage for reading the current status indication in the intermediate storage stage into said output register synchronized to said second reference clock in response to a read request signal being input into said output storage stage;
- and
- c2) said intermediate storage stage further comprises a synchronization stage for generating a hold signal to be applied to an intermediate register of said intermediate storage stage for holding a current status indication in said intermediate register and for blocking a shifting of a new indication from said input to said intermediate storage stage.
Dependencies are inferred from the claim text.