Substantially temperature independent delay chain
AssigneeMacronix International Co., Ltd.
InventorChung Kuang Chen
Life of this patent
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Abstract
Methods and apparatuses are discussed for generating a temperature compensated signal, used for example to provide a signal with a delay within a pre-specified range over a range of temperatures to a sense amplifier of a memory array. In response to a start signal, a varying signal is generated. A clock signal causes additional loads of impedance to be coupled to the varying signal, for example via control circuitry generating temperature compensating signals.
Claims47
A method for generating a temperature compensated signal with an integrated circuit while using the integrated circuit, comprising:
- generating a varying signal on a portion of the integrated circuit in response to a start signal at a first time, the varying signal having a varying characteristic;
- generating a clock signal on the integrated circuit, wherein the clock signal varies with temperature;
- applying the clock signal to a plurality of loads on the integrated circuit;
- in response to the clock signal, coupling additional impedance of the plurality of loads to the portion of the circuit with the varying signal;
- and
- in response to the varying characteristic of the varying signal reaching a reference level, generating a signal on the integrated circuit at a second time, the signal characterized by a delay within a pre-specified range between the first time and the second time over a temperature range.
An integrated circuit device, comprising:
- a circuit carrying, in response to a start signal at a first time, a varying signal having a varying characteristic;
- clock circuitry configured to generate a clock signal varying with temperature;
- a plurality of impedances coupled to the clock circuitry and the circuit, the plurality of impedances having a total impedance that increases in response to the clock signal;
- and
- an output coupled to the circuit, the output passing at a second time a signal characterized by a delay within a pre-specified range between the first time and the second time over a temperature range.
A method of manufacturing an integrated circuit device, comprising:
- providing a semiconductor substrate;
- forming a circuit carrying, in response to a start signal at a first time, a varying signal having a varying characteristic;
- forming clock circuitry on the semiconductor substrate configured to generate a clock signal varying with temperature;
- forming a plurality of impedances on the semiconductor substrate coupled to the clock circuitry and the circuit, the plurality of impedances having a total impedance that increases in response to the clock signal;
- and
- forming an output on the semiconductor substrate coupled to the circuit, the output passing at a second time a signal characterized by a delay within a pre-specified range between the first time and the second time over a temperature range.
A method of generating a temperature compensated output on an integrated circuit, comprising:
- in response to a start signal at a first time on an integrated circuit,
- triggering a first circuit of the integrated circuit to perform a main function of the first circuit and generate a main function output signal;
- and
- triggering a second circuit of the integrated circuit to generate a second signal at a second time, the second signal having a delay within a pre-specified range between the first time and the second time, wherein the delay is independent of a timing of the main function output;
- and
- allowing the main function output signal to pass to other circuitry on the integrated circuit after the delay.
An integrated circuit device, comprising:
- a first circuit performing, in response to a start signal at a first time, a main function of the first circuit and generating a main function output signal;
- a second circuit generating, in response to the start signal, a second signal at a second time, the second signal having a delay within a pre-specified range between the first time and the second time, wherein the delay is independent of a timing of the main function output;
- a third circuit coupled to the first circuit and the second circuit, the third circuit receiving the main function output signal and the second signal, and allowing the main function output signal to pass to other circuitry on the integrated circuit after the delay.
Dependencies are inferred from the claim text.