US 7,216,198 B2Granted

DRAM with super self-refresh and error correction for extended period between refresh operations

AssigneesElpida Memory, Inc., Hitachi ULSI Systems Co., Ltd., Hitachi, Ltd.

InventorsYutaka Ito, Takayuki Aisu, Yukihide Suzuki

Life of this patent

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Abstract

In a semiconductor integrated circuit device, a command decoder is adapted to receive not only an external command but also an internal command. An ECC controller has a command generator and an address generator. When the command decoder decodes an external entry command, the command generator instructs encoding to an ECC-CODEC circuit and the address generator sequentially produces addresses which are supplied to a memory array. The ECC-CODEC circuit produces check bits for error detection/correction with reference to information data of the memory array. Upon completion of an encoding operation of writing the check bits into a predetermined region of the memory array, the ECC controller delivers an end signal to the command decoder as the internal command to make a super self-refresh control circuit start a super self-refresh operation.

Claims12

Dependent claims

A semiconductor integrated circuit device having a dynamic RAM, said dynamic RAM comprising a memory array, a RAM control section, an ECC-codec circuit, and an ECC controller, said RAM control section comprising a command decoding section responsive to an external command from the outside of said dynamic RAM for decoding the external command and a super self-refresh control circuit, said super self-refresh control circuit being contained within said RAM control section, wherein:

said command decoding section is also adapted to receive an internal command generated inside said dynamic RAM and to decode the internal command;
said ECC controller comprises a command generating section and an address generating section, said address generating section being contained within said ECC controller;
said command decoding section delivers a start instruction signal representative of encoding to said ECC controller when an entry command is decoded as the external command;
said command generating section of said ECC controller delivers, upon reception of the start instruction signal, a first operation mode signal representative of the encoding and simultaneously makes said address generating section of said ECC controller sequentially generate addresses corresponding to operation timings of the first operation mode signal and supplies the addresses to said memory array;
said ECC-codec circuit carries out, upon reception of the first operation mode signal, an encoding operation of producing a check bit for error detection/correction with reference to information data stored in said memory array and writes the check bit into a predetermined region of said memory array;
said command generating section of said ECC controller delivers, upon completion of the encoding operation by said ECC-codec circuit, a first end signal as the internal command to said command decoding section;
said super self-refresh control circuit of said RAM control section starts, when said command decoding section receives and decodes the first end signal as the internal command, a super self-refresh operation which has a refresh cycle lengthened within an allowable range of error occurrence by an error correcting operation using the check bit.

4 more elements

A semiconductor integrated circuit device having a dynamic RAM, said dynamic RAM comprising a memory array, a RAM control section, an error correction circuit, and a BIST (built-in self-test) controller, said RAM control section comprising a command decoding section responsive to an external command from the outside of said dynamic RAM for decoding the external command, wherein:

said command decoding section is also adapted to receive an internal command generated inside said dynamic RAM and to decode the internal command;
said BIST controller comprises a command generating section and an address generating section, said address generating section being contained within said BIST controller;
said command decoding section delivers a start instruction signal representative of checking to said BIST controller when a BIST entry command is decoded as the external command;
said command generating section of said BIST controller delivers, upon reception of the start instruction signal, an operation mode signal representative of the checking and simultaneously makes said address generating section of said BIST controller sequentially generate addresses corresponding to operation timings of the operation mode signal and supplies the addresses to said memory array;
said error correction circuit produces, upon reception of the operation mode signal, write data corresponding to the addresses sequentially generated, writes the write data into a predetermined region or an entire region of said memory array, produces expectation data corresponding to the addresses sequentially generated, compares the expectation data with information data read from said memory array, detects an error in the information data, and, upon completion of error detection, delivers an end signal as the internal command to said command decoding section;
delivery of the start instruction signal being stopped when said command decoding section receives and decodes the end signal as the internal command.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/699,223Filed 30 Oct 2003
Priority: JP 2002/31531930 Oct 2002
Published: US 2004/0221098 A14 Nov 2004
Granted: 8 May 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G11C 29/42
Response verification devices: using error correcting codes [ECC] or parity check
G06F 11/106
Using arrangements adapted for a specific error detection or correction feature: correcting systematically all correctable errors, i.e. scrubbing
G11C 7/02
Arrangements for writing information into, or reading information out from, a digital store: with means for avoiding parasitic signals
G11C 7/1006
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data managing, e.g. manipulating data before…