Multi-layered memory cell structure

A multi-layered memory device for storing data and subsequently reading out the stored data, said memory device utilizing a plurality of existing stacked process conductor layers, said memory device comprising:

• (a) plurality of memory cells arranged in columns and rows, each memory cell including at least one transistor, each transistor being adapted to store information;
• (b) plurality of wordlines corresponding to the plurality of rows, each wordline being used in common in each row of said memory cells, at least one of said wordlines being connected to a corresponding memory cell in the column of memory cells;
• (c) plurality of bitlines, said bitlines arranged substantially orthogonal to said wordlines, at least one of said bitlines being used in common for data read-out along a column of memory cells;
• (d) at least one via-stack, said via-stack comprising a plurality of vias positioned to connect adjacent conduction layers, said via-stack being arranged in close proximity to at least one memory cell, said via-stack being adapted to electrically connect at least one transistor within at least one memory cell to at least one of the existing stacked process conductor layers;
• wherein said existing stacked process conductor layers are used to implement within the multi-layered memory device, at least one of an additional wordline as defined in (b) and an additional bitline as defined in (c).