US 7,215,201 B2 · Integrated circuit having a low power, gain-enhanced, low noise amplifying circuit

Abstract

An amplifying circuit includes an n-type transistor having a source, a gate coupled to a first bias voltage, and a drain coupled to a first supply voltage through a first impedance circuit. A p-type transistor of the circuit has a source coupled to the source of the n-type transistor, a gate coupled to a second bias voltage, and a drain coupled to a second supply voltage through a second impedance circuit. A first differential input is coupled to the gate of the n-type transistor through a first capacitor and to the gate of the p-type transistor through a second capacitor. A second differential input is coupled to the sources of the n-type and the p-type transistors. A third capacitor has a first end coupled to the drain of the n-type transistor, and a fourth capacitor has a first end coupled to the drain of the p-type transistor and a second end coupled to a second end of the third capacitor. An output of the amplifier circuit is provided at the second ends of the third and the fourth capacitors. The n-type transistor and the first impedance circuit serve as a common-source amplifier for a signal at the first differential input and as a common-gate amplifier for the signal at the second differential input. Similarly, the p-type transistor and the second impedance circuit serve as a common-source amplifier for the signal at the first differential input and as a common-gate amplifier for the signal at the second differential input.

Claims27

Dependent claims

An amplifier circuit, comprising:

an n-type transistor having:
a source;
a gate coupled to a first bias voltage;
a drain coupled to a first supply rail voltage through a first impedance circuit;
a p-type transistor having:
a source coupled to the source of the n-type transistor;
a gate coupled to a second bias voltage;
a drain coupled to a second supply rail voltage through a second impedance circuit;
a first differential input coupled to the gate of the n-type transistor through a first capacitor and to the gate of the p-type transistor through a second capacitor;
a second differential input coupled to the sources of the n-type and the p-type transistors;
a third capacitor having a first end coupled to the drain of the n-type transistor;
a fourth capacitor having a first end coupled to the drain of the p-type transistor and a second end coupled to a second end of the third capacitor;
and
an output of the amplifier circuit being provided at the second ends of the third and the fourth capacitors.

11 more elements

A differential amplifier, comprising:

a first n-channel transistor having:
a source;
a gate coupled to a first bias voltage;
a drain coupled to a first supply rail voltage through a first impedance circuit;
a first p-channel transistor having:
a source coupled to the source of the first n-channel transistor;
a gate coupled to a second bias voltage;
a drain coupled to a second supply rail voltage through a second impedance circuit;
a first differential input coupled to the gate of the first n-channel transistor through a first capacitor and to the gate of the first p-channel transistor through a second capacitor;
a second differential input coupled to the sources of the first n-channel and the first p-channel transistors;
a third capacitor having a first end coupled to the drain of the first n-channel transistor;
a fourth capacitor having a first end coupled to the drain of the first p-channel transistor and a second end coupled to a second end of the third capacitor;
and
a first differential output being provided at the second ends of the third and the fourth capacitors;
a second n-channel transistor having:
a source;
a gate coupled to the first bias voltage;
a drain coupled to the first supply rail voltage through a third impedance circuit;
a second p-channel transistor having:
a source coupled to the source of the second n-channel transistor;
a gate coupled to the second bias voltage;
a drain coupled to the second supply rail voltage through a fourth impedance circuit;
the first differential input being coupled to the sources of the second n-channel and the second p-channel transistors;
the second differential input being coupled to the gate of the second n-channel transistor through a fifth capacitor and to the gate of the second p-channel transistor through a sixth capacitor;
a seventh capacitor having a first end coupled to the drain of the second n-channel transistor;
an eighth capacitor having a first end coupled to the drain of the second p-channel transistor and a second end coupled to a second end of the seventh capacitor;
and
a second differential output being provided at the second ends of the seventh and the eighth capacitors.

25 more elements

An integrated circuit (IC), comprising:

a first differential input externally exposed on the IC;
a second differential input externally exposed on the IC;
an n-type transistor having:
a source;
a gate coupled to a first bias voltage;
a drain coupled to a first supply rail voltage through a first impedance circuit;
a p-type transistor having:
a source coupled to the source of the n-type transistor;
a gate coupled to a second bias voltage;
a drain coupled to a second supply rail voltage through a second impedance circuit;
the first differential input being coupled to the gate of the n-type transistor through a first capacitor and to the gate of the p-type transistor through a second capacitor;
the second differential input being coupled to the sources of the n-type and the p-type transistors;
a third capacitor having a first end coupled to the drain of the n-type transistor;
a fourth capacitor having a first end coupled to the drain of the p-type transistor and a second end coupled to a second end of the third capacitor;
and
an output being provided at the second ends of the third and the fourth capacitors.

13 more elements

Dependencies are inferred from the claim text.

Integrated circuit having a low power, gain-enhanced, low noise amplifying circuit

Life of this patent

Integrated circuit having a low power, gain-enhanced, low noise amplifying circuit

Life of this patent

Abstract

Claims27