Semiconductor memory

A hand-held terminal comprising:

• a semiconductor memory chip to be mounted on the hand-held terminal, the semiconductor chip comprising;
• a plurality of memory cells;
• a bit line connected to the memory cells;
• a sense amplifier connected to the bit line;
• a partial area composed of a first memory cell of the memory cells;
• and
• an operation control circuit configured to operate any of the memory cells selected in accordance with an address signal, during a normal operation mode in which a read operation or a write operation are performed, and configured to keep latching data retained by said first memory cell into the sense amplifier, during a low power consumption mode in which data only in said first memory cell is retained.

A semiconductor chip comprising:

• a plurality of memory cells;
• a bit line connected to the memory cells;
• a sense amplifier connected to the bit line;
• a partial area composed of a first memory cell of the memory cells;
• and
• an operation control circuit configured to operate any of the memory cells selected in accordance with an address signal, during a normal operation mode in which a read operation or a write operation are performed, and configured to latch data retained by said first memory cell into the sense amplifier, during a partial mode in which data only in said first memory cell is retained.

A semiconductor chip comprising:

• a memory array that includes a plurality of memory cells arranged in a matrix, the plurality of memory cells composed of a first group of memory cells as a partial area and a second group of memory cells;
• a plurality of bit lines connected to the first and second group of memory cells;
• a plurality of sense amplifiers connected to the plurality of bit lines;
• a mode register that is set to either a first value indicating a normal operation mode or a second value indicating a low power consumption mode;
• and
• an operation control circuit configured to operate any of the first and second group of memory cells selected in accordance with an address signal, during the normal operation mode in which a read operation or a write operation are performed, and configured to latch data retained by the first group of memory cells into the corresponding sense amplifier, during the low power consumption mode in which data only in said first group of memory cells are retained.

A semiconductor chip comprising:

• a memory cell array that includes a plurality of volatile memory cells arranged in a matrix;
• a plurality of sense amplifiers connected to the bit lines;
• a mode register that is set to either a first value indicating a normal operation mode or a second value indicating a low power mode;
• and
• an operation control circuit configured to select any one of the memory cells in the memory cell array in accordance with an address signal when the mode register is set to the first value, and configured to select a partial area corresponding to specific memory cells in the memory cell array when the mode register is set to the second value in order to retain only data of the specific memory cells in the corresponding sense amplifier without a refresh operation.

A semiconductor chip comprising:

• a memory cell array that includes a plurality of memory cells arranged in a matrix;
• a plurality of word lines connected to the memory cells;
• a plurality of bit lines connected to the memory cells;
• a plurality of sense amplifiers connected to the bit lines;
• a mode register that designates either a first value indicating a normal operation mode or a second value indicating a partial mode;
• and
• an operation control circuit configured to select at least one of the word lines in accordance with an address signal when the mode register designates the first value, and configured to select a specific word line among the plurality of the word lines when the mode register designates the second value in order to latch only data of the memory cells connected to the specific word line into the corresponding sense amplifiers.

A semiconductor chip comprising:

• a memory cell array that includes a plurality of volatile memory cells arranged in a matrix, in which the memory cells array includes a plurality of word lines, a plurality of bit lines and a plurality of sense amplifiers;
• an operation control circuit coupled to the memory cell array and configured to operate the memory cells by controlling the word line, the bit lines and the sense amplifiers;
• a refresh control circuit configured to output a refresh request signal generated within the chip to the operation control circuit in order to refresh the memory cells;
• and
• a mode register that designates either a first value indicating a normal operation mode or a second value indicating a partial mode, the refresh request signal is invalid during the partial mode, wherein
• the operation control circuit operates the memory cells to refresh the memory cells in accordance with the refresh request signal when the mode register designates the normal operation and operates specific memory cells among the memory cells to latch only data of the specific memory cells into the corresponding sense amplifiers when the mode register designates the partial mode.