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US 7,209,395 B2Granted
Low leakage and leakage tolerant stack free multi-ported register file
AssigneeIntel Corporation
InventorsSteven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy
Life of this patent
Estimating the term…
Abstract
A device includes a number of memory cells. Each of the memory cells includes a transistor stack coupled to a bit line. A value of a charge on the bit line during an access mode represents a value of data stored in an accessed memory cell. During a non-access mode, all transistors of the transistor stack are turned off to save power. The transistors are turn off regardless of the value of the data stored in the memory cells.
Claims29
A device comprising:
- a bit line;
- a transistor stack including a first transistor and a second transistor coupled between the bit line and a supply node;
- a memory unit including a storage node;
- and
- an isolation unit to isolate the transistor stack from the memory unit, the isolation unit including a pass gate to couple a gate of the first transistor to a gate of the second transistor based on a bit value of the storage node.
2 more elements
A device comprising:
- a bit line;
- a transistor stack coupled between the bit line and a supply node, the transistor stack including a number of transistors coupled in series between the bit line and the supply node, the number of transistors including a first transistor and a second transistor;
- a memory unit;
- and
- an isolation unit to isolate the transistor stack from the memory unit, wherein the isolation unit includes a first switch to conditionally couple a gate of the first transistor to a gate of the second transistor based on a bit value of the memory unit, and a second switch to turn off one of the first and second transistors based on the bit value of the memory unit.
2 more elements
A device comprising:
- a plurality of bit lines;
- a plurality of select lines;
- a plurality of first memory cells, each of the first memory cells coupled to a first bit line of the plurality of bit lines;
- and
- a plurality of second memory cells, each of the second memory cells coupled to a second bit line of the plurality of the bit lines, wherein each memory cell of the first memory cells and the second memory cells includes a transistor stack having a first transistor and a second transistor coupled between one of the bit lines and a supply node, a memory unit including a storage node, and an isolation unit coupled between the transistor stack and the memory units wherein the isolation unit includes a pass gate responsive to a bit value of the storage node to couple a gate of the first transistor and a gate of the second transistor to one of the select lines.
2 more elements
A device comprising;
- a plurality of bit lines;
- a plurality of select lines;
- a plurality of first memory cells, each of the first memory cells coupled to a first bit line of the plurality of bit lines;
- and
- a plurality of second memory cells, each of the second memory cells coupled to a second bit line of the plurality of the bit lines, wherein each memory cell of the first memory cells and the second memory cells includes a transistor stack coupled between one of the bit lines and a supply node, a memory unit, and an isolation unit coupled between the transistor stack and the memory unit, the transistor stack including a first transistor and a second transistor coupled in series with the first transistor between the bit line and the supply node, the memory unit including a first inverter including an input node, and an output node, and a second inverter including an input node coupled to the output node of the first inverter, and an output node coupled to the input node of the first inverter, wherein the isolation unit includes:
- a pass gate including a first pass gate control node coupled to the input node of the first inverter, a second pass gate control node coupled to the output of the first inverter, a first pass node coupled to a gate of the first transistor of the transistor stack, and a second pass node coupled to a gate of the second transistor of the transistor stack;
- and
- a transistor including a gate coupled to the second pass gate control node, a drain coupled to second pass node, and a source coupled to the supply node.
5 more elements
A system comprising:
- a processing unit;
- and
- a cache memory device coupled to the processing unit, at least one of the processing unit and the cache memory device including a register file, the register file including:
- a bit line;
- a transistor stack including a number of transistors coupled between the bit line and a supply node;
- a memory unit to store complementary bit values of a data bit;
- and
- an isolation unit coupled between the transistor stack and the memory unit, wherein the isolation unit includes a first switch to conditionally couple gates of the transistors of the transistor stack based on a first bit value of the complementary bit values, and a switch to turn off one of the transistors based on the first bit value of the complementary bit values.
5 more elements
A method comprising:
- holding a bit line at a first value when a select line coupled to a memory cell is activated and a memory unit of a memory cell has a first bit value;
- creating a conductive path between the bit line and a supply node to change the first value of the bit line to a second value when the select line is activated and the memory unit of the memory cell has a second bit value, wherein the conductive path runs through a first transistor and a second transistor of a transistor stack of the memory cell, and wherein creating the conductive path includes coupling a gate of the first transistor to a gate of the second transistor;
- and
- isolating the transistor stack from the memory unit of the memory cell when the select line is deactivated.
1 more element
Dependencies are inferred from the claim text.