Method and system for sampling a signal

A method comprising:

• clocking a digital circuit with a digital clock signal having an associated clock period;
• receiving an input clock having a fixed phase relationship with respect to the digital clock signal;
• generating a sample clock having a first sampling edge corresponding to a first relative offset within the clock period and a next sampling edge corresponding to a different relative offset within the clock period;
• sampling a designated signal in response to the first sampling edge;
• and
• sampling the designated signal in response to the next sampling edge.

A system comprising:

• a digital circuit clocked by a digital clock signal having an associated clock period;
• a sample clock generation circuit configured to receive an input clock having a fixed phase relationship with respect to the digital clock signal, wherein the sample clock generation circuit is further configured to generate a plurality of sample clock signals each having a sampling edge corresponding to a different relative offset within the clock period;
• and
• a sampling circuit coupled to the sample clock generation circuit and configured to sample a designated signal in response to each of the sampling edges during a sample cycle.

A method comprising:

• clocking a digital circuit with a digital clock signal having an associated clock period;
• receiving an input clock having a fixed phase relationship with respect to the digital clock signal;
• generating a plurality of sample clock signals each having a sampling edge corresponding to a different relative offset within the clock period;
• and
• sample a designated signal in response to each of the sampling edges during a sample cycle.