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US 7,208,751 B2Granted
Non-volatile semiconductor memory device allowing shrinking of memory cell
AssigneeRenesas Technology Corp.
InventorTsukasa Ooishi
Life of this patent
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AssigneeRenesas Technology Corp.
InventorTsukasa Ooishi
Estimating the term…
Dummy cells are disposed in alignment with memory cells arranged in rows and columns in a memory array. The memory cell includes a variable resistance element and a select transistor having a collector connected to a substrate region and selecting the variable resistance element in response to a row select signal. Corresponding to a row of memory cells, there is provided a word line connecting to memory cells on corresponding row and transmitting the row select signal, and a word line shunting line electrically connected at predetermined intervals to each word line. Moreover, corresponding to a row of dummy cells and a column of dummy cells, there is provided substrate shunt lines electrically connected to the substrate region. The voltage distribution in the substrate region is eliminated to achieve stable operating characteristics of the memory cell transistor. In addition, a word line is driven at high speed by a word line shunt structure.
A non-volatile semiconductor memory device comprising:
A non-volatile semiconductor memory device comprising:
A non-volatile semiconductor memory device comprising:
A non-volatile memory device comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Using resistive RAM [RRAM] elements: comprising amorphous/crystalline phase transition cells
Details of stores covered by group G11C11/00: disposition of storage elements, e.g. in the form of a matrix array
Arrangements for writing information into, or reading information out from, a digital store: dummy cell management; Sense reference voltage generators
Resistance change memory devices, e.g. resistive RAM [ReRAM] devices: phase change RAM [PCRAM, PRAM] devices
Term ended 22 Mar 2023 (estimated)
1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices, particularly to a phase change memory in which the crystalline state changes according to the stored data. More specifically, the present invention relates to the technique for shrinking the components of a phase change memory.
2. Description of the Background Art
FIG. 1 schematically shows the layout of a memory array in a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 schematically shows a sectional structure taken along line L2—L2 of FIG. 1.
FIG. 3 schematically shows a sectional structure taken along line L3—L3 of FIG. 1.
First Embodiment
FIG. 1 schematically shows the layout of the memory array of a non-volatile semiconductor memory device according to a first embodiment of the present invention. FIG. 1 shows the layout of memory cells MC arranged in three rows and three columns. Referring to FIG. 1, word lines WL0–WL2 are provided corresponding to the respective rows of memory cells MC, and bit lines BL0–BL2 are disposed corresponding to the respective columns of memory cells MC, as in the conventional example. Word lines WL0–WL2 are each formed of an impurity layer located at the surface of a semiconductor substrate. Word lines WL0–WL2 each extend continuously in the row direction.
Memory cell MC includes a chalcogenide film CG of a rectangular feature coupled to bit line BL (indicating generically BL0–BL2), a heater HT for heating chalcogenide film CG, and a transistor element formed between this heater and a substrate region not shown. In FIG. 1, the transistor element included in memory cell MC is not depicted.