Pitch multiplication process

A method of forming a semiconductor device comprising:

• forming a patterned mask layer on a silicon layer, wherein the patterned mask layer has a first line width;
• anisotropically etching the silicon layer to form a first plurality of sloped sidewalls;
• forming an oxide layer on the first plurality of sloped sidewalls;
• etching the patterned mask layer so that the patterned mask layer has a second line width less than the first line width;
• anisotropically etching the first silicon layer to form a second plurality of sloped sidewalls;
• forming an oxide layer on the second plurality of sloped sidewalls;
• removing the patterned mask layer;
• and
• anisotropically etching the silicon layer to form a third plurality of sloped sidewalls, wherein the first plurality sloped sidewalls, the second plurality of sloped walls, and the third plurality of sloped sidewalls form a triangular wire channel array.

A method of forming a semiconductor device comprising:

• forming a patterned mask layer on a silicon layer, wherein the patterned mask layer has a line width;
• anisotropically etching the silicon layer to expose a first plurality of (111) planes;
• forming an oxide layer on the first plurality of (111) planes;
• etching the patterned mask layer to decrease the line width;
• anisotropically etching the silicon layer to expose a second plurality of (111) planes;
• forming an oxide layer on the second plurality of (111) planes;
• removing the patterned mask layer;
• and
• anisotropically etching the silicon layer to expose a third plurality of (111) planes, wherein the first plurality of (111) planes, the second plurality of (111) planes, and third plurality of (111) planes form a triangular wire channel array.