On-chip transistor degradation monitoring

A method in an integrated circuit with functional blocks, the method comprising:

• generating a free-running oscillation signal to degrade transistors in a first ring oscillator,
• selectively generating a reference oscillation signal in a second ring oscillator, and
• periodically comparing the free-running oscillation signal with the reference oscillation signal to characterize the transistor degradation in the transistors of the integrated circuit, the transistor degradation including at least one of p-channel metal oxide semiconductor field effect transistor bias temperature (PMOS BT) degradation and hot electron transistor degradation;
• wherein the first ring oscillator and the second ring oscillator are located in the same area of the integrated circuit.

A system comprising:

• a processor for executing instructions and processing data, transistors of the processor to experience transistor degradation over time;
• an integrated on-chip characterization circuit to determine a measure of transistor degradation in the transistors of the processor, the integrated on-chip characterization circuit including
• at least one free-running ring oscillator to generate a free-running oscillating signal,
• at least one selectively enabled ring oscillator to generate a reference oscillating signal, and
• a comparison circuit coupled to the selectively enabled ring oscillator and the free-running ring oscillator, the comparison circuit to periodically determine the measure of transistor degradation in the transistors of the processor, the transistor degradation including at least one of p-channel metal oxide semiconductor field effect transistor bias temperature (PMOS BT) degradation and hot electron transistor degradation;
• wherein the at least one selectively enabled ring oscillator and the at least one free-running ring oscillator are located in the same area of the integrated circuit.

An enabable ring oscillator comprising:

• an odd number of p-channel field effect transistors (PFETs) each having a gate, a drain, and a source;
• an odd number of n-channel field effect transistors (NFETs) each having a gate, a drain, and a source;
• the odd number of PFETs and the odd number of NFETs coupled together to form a daisy chain series of inverters with a switchable power supply;
• and
• wherein the drain of a last PFET of the odd number of PFETs and the drain of a last NFET of the odd number of NFETs coupled together to couple to gates of a first PFET of the add number of PFETs and first NFET of the odd number of NFETs;
• wherein the enabable ring oscillator to provide a reference frequency to a comparison circuit for a measurement of at least one of p-channel metal oxide semiconductor field effect transistor bias temperature (PMOS BT) degradation and hot electron transistor degradation.