Adjusting power consumption of digital circuitry relative to critical path circuit having the largest propagation delay error
AssigneeWestern Digital Technologies, Inc.
InventorGeorge J. Bennett
Life of this patent
Estimating the term…
Abstract
A method and apparatus is disclosed for adjusting at least one of a supply voltage and a clocking frequency applied to digital circuitry of a computing device, wherein the digital circuitry comprises a plurality of critical path circuits and a corresponding plurality of propagation delay error circuits. Each propagation delay error circuit generates a propagation delay error signal representing an error in propagation delay for the corresponding critical path circuit. The computing device further comprises a voting circuit for comparing the propagation delay error signals in order to select the largest propagation delay error signal for use in adjusting the at least one of the supply voltage and clocking frequency.
Claims12
A computing device comprising:
- (a) digital circuitry including a plurality of critical path circuits and a corresponding plurality of propagation delay error circuits, wherein each propagation delay error circuit generates a propagation delay error signal representing an error in propagation delay for the corresponding critical path circuit;
- (b) a voting circuit for comparing the propagation delay error signals in order to select the largest propagation delay error signal;
- and
- (c) an adjustable circuit, responsive to the largest propagation delay error signal, for adjusting at least one of a supply voltage and a clocking frequency applied to the critical path circuits.
A method of adjusting at least one of a supply voltage and a clocking frequency applied to digital circuitry of a computing device, the digital circuitry comprising a plurality of critical path circuits, the method comprising the steps of:
- (a) generating a plurality of propagation delay error signals each representing an error in propagation delay for a corresponding one of the critical path circuits;
- (b) comparing the propagation delay error signals in order to select the largest propagation delay error signal;
- and
- (c) adjusting at least one of the supply voltage and the clocking frequency in response to the largest propagation delay error signal.
Dependencies are inferred from the claim text.