Phase error correction circuit for a high speed frequency synthesizer

An integrated circuit comprising:

• a phase detector having a first input for receiving a reference signal;
• a numerically controlled oscillator coupled to the phase detector and having an overflow output and a remainder output;
• a phase error correction circuit coupled to the numerically controlled oscillator and having an output wherein the phase error correction circuit comprises:
• a coarse phase error correction stage having first input coupled to the overflow output of the numerically controlled oscillator, a second input coupled to the remainder output of the numerically controlled oscillator, and a coarse phase error corrected overflow output;
• and
• a fine phase error correction stage having a first input coupled to the coarse phase error corrected overflow output of the coarse phase error correction stage and a second input coupled to the remainder output of the numerically controlled oscillator;
• and
• a divider coupled between the phase error correction circuit and the phase detector.

A method of providing a clock signal comprising:

• providing a phase increment signal;
• accumulating the phase increment signal;
• each time the accumulated phase increment signal reaches a first threshold, toggling an overflow signal;
• and
• using the accumulated phase increment signal to retime the overflow signal,
• wherein the phase increment signal is accumulated each cycle of a clock, and
• wherein the overflow signal is retimed in two stages comprising:
• during the first stage, retiming the overflow signal to within a first duration;
• and
• during the second stage, retiming the overflow signal to within a second duration, the second duration shorter than the first duration.

An integrated circuit comprising:

• an NCO configured to receive increment information and provide an overflow signal and a remainder signal;
• and
• a dynamic phase mixer configured to retime the overflow signal using the remainder signal to generate a pixel clock wherein the dynamic phase mixer comprises:
• a first stage to provide a coarse phase-error correction to the overflow signal;
• and
• a second stage to provide a fine phase-error correction to the coarse corrected overflow signal,
• wherein the NCO and dynamic phase mixer operate open loop.