Method and system for routing in low density parity check (LDPC) decoders
AssigneeThe DirectTV Group, Inc.
InventorsMustafa Eroz, Lin-Nan Lee, Feng-Wen Sun, Bob Cassagnol, Adam Von Ancken
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Abstract
An approach is provided for decoding a low density parity check (LDPC) coded signal. Edge values associated with a structured parity check matrix used to generate the LDPC coded signal are retrieved from memory. The edge values specify the relationship of bit nodes and check nodes, and are stored within memory according to a predetermined scheme that permits concurrent retrieval of a set of the edge values. A decoded signal corresponding to the LDPC coded signal is output based on the retrieved edge values.
Claims18
A method for decoding a low density parity check (LDPC) coded signal, the method comprising:
- retrieving edge values associated with a structured parity check matrix used to generate the LDPC coded signal, wherein the edge values specify relationship of bit nodes and check nodes, and are stored according to a predetermined scheme that permits concurrent retrieval of a set of the edge values, the predetermined scheme specifies contiguous physical memory locations for the set of edge values;
- and
- outputting a decoded signal corresponding to the LDPC coded signal based on the retrieved edge values;
- wherein the set of edge values is retrieved in a single clock cycle of a processor coupled to the memory, and is adjacent to a group of M bit nodes or M check nodes, where M is the number of parallel processing engines.
A decoder for decoding a low density parity check (LDPC) coded signal comprising:
- means for retrieving edge values associated with a structured parity check matrix used to generate the LDPC coded signal;
- memory for storing the edge values according to a predetermined scheme that permits concurrent retrieval of a set of the edge values, wherein the edge values specify relationship of bit nodes and check nodes, the predetermined scheme specifies contiguous physical memory locations for the set of edge values;
- and
- means for outputting a decoded signal corresponding to the LDPC coded signal based on the retrieved edge values;
- a processor coupled to the memory, wherein the set of edge values is retrieved in a single clock cycle of the processor and is adjacent to a group of M bit nodes or M check nodes, where M is the number of parallel processing engines.
A memory accessible by a low density parity check (LDPC) decoder for decoding a LDPC coded signal, comprising:
- a first portion storing a first group of edge values associated with a structured parity check matrix used to generate the LDPC coded signal, the first group of edges being connected to bit nodes of n degrees;
- a second portion storing a second group of edge values associated with the structured parity check matrix used to generate the LDPC coded signal, the second group of edges being connected to bit nodes of greater than n degrees, wherein a set of edge values from the first group or the second group is retrieved to output a decoded signal;
- and
- a processor coupled to the memory, wherein the set of edge values is retrieved in a single clock cycle of the processor and is adjacent to a group of M bit nodes or M check nodes, where M is the number of parallel processing engines.
Dependencies are inferred from the claim text.