Error detection, documentation, and correction in a flash memory device

A flash memory device comprising:

• a primary memory array comprising a plurality of non-volatile memory cells;
• an error documentation memory array of non-volatile memory cells that stores documentation data regarding a first over-programmed memory cell in the primary memory array, the documentation data comprising a data offset indicating a quantity of states between a desired data and an actual programmed data of the first over-programmed memory cell;
• and
• a controller circuit for generating memory control signals and adapted to execute an error detection, documentation, and correction method comprising:
• detecting the first over-programmed memory cell;
• programming the first over-programmed memory cell to a subsequent state;
• and
• storing, in the error documentation memory array, first documentation data regarding first over-programmed memory cell.

An electronic system comprising:

• a processor that controls operation of the electronic system;
• and
• a flash memory device, coupled to the processor, comprising:
• a controller circuit for generating memory control signals;
• a primary memory array coupled to the controller circuit, the primary memory array comprising a plurality of non-volatile memory cells;
• and
• an error documentation memory array of non-volatile memory cells, coupled to the controller circuit, that stores documentation data regarding a first over-programmed memory cell in the primary memory array, the documentation data comprising a data offset indicating a quantity of states between a desired data and an actual programmed data of the first over-programmed memory cell.