Strained finFETs and method of manufacture
AssigneeInternational Business Machines Corporation
InventorsDureseti Chidambarrao, Omer H. Dokumaci, Oleg G. Gluschenkov
Life of this patent
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Abstract
A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material form a first island and second island at an pFET region and a nFET region, respectively. A tensile hard mask is formed on the first and the second island layer prior to forming finFETs. An Si epitaxial layer is grown on the sidewalls of the finFETs with the hard mask, now a capping layer which is under tension, preventing lateral buckling of the nFET fin.
Claims26
A method of manufacturing a structure, comprising the steps of:
- forming a first island of material having a first lattice constant;
- forming a second island of material having a second lattice constant;
- providing a mask over the first island and the second island which is used to form a tensile capping layer;
- and
- forming at least a first finFET and a second finFET from the first island and the second island,
- wherein the tensile capping layer prevents buckling of one of the first and second finFET.
A method of manufacturing a semiconductor structure, comprising the steps of:
- forming shallow trench isolation (STI) in a substrate with a first material;
- forming a first island associated with a pFET region and a second island associated with an nFET region;
- providing a hard mask in tensile stress over the pFET region and the nFET region;
- forming a pFET fin and an nFET fin with a capping layer of the hard mask in the pFET region and the nFET region, respectively;
- and
- growing sidewalls on the pFET fin and the nFET fin, wherein the capping layer prevents buckling of the nFET fin during sidewall growth.
A method, comprising:
- forming a structure comprising a shallow trench isolation (STI) between a first region and a second region;
- depositing an epitaxial Ge material over a surface of structure;
- providing an nFET hard mask on a portion of the Ge layer over the first region;
- etching an exposed portion of the Ge layer;
- stripping the nFET hard mask;
- depositing a Si:C or C layer over the epitaxially deposited Ge material over the second region;
- depositing a pFET hard mask on a portion of the Si:C or C layer on the first region;
- etching exposed portions of the Si:C or C layer;
- stripping the pFET mask;
- and
- annealing the formed structure,
- wherein during the annealing, for an nFET device, the deposited Ge layer is mixed into an underlying SOI film to form an island of substantially SiGe material and, for a pFET device, the deposited Si:C layer is mixed into the underlying SOI film forming an island of substantially Si:C material.
Dependencies are inferred from the claim text.