Semiconductor work-in-process (WIP) dispatch management methods and systems

A method of semiconductor work-in-process (WIP) dispatch management comprising using a computer to perform the steps of:

• acquiring information regarding a plurality of wafer lots to be processed in a process node by the computer;
• determining which wafer lot requires processing prior to the other wafer lots by analyzing a load of a plurality of successive process nodes for each wafer lot by the computer;
• and
• directing a transport system to transport the determined wafer lot to the process node by the computer,
• wherein the acquired information regarding a first wafer lot and a second wafer lot to be processed, and the step of determining one of the wafer lots to be processed earlier than the other wafer lot further comprises:
• determining a plurality of first successive process nodes for the first wafer lot, and a plurality of second successive process nodes for the second wafer lot;
• calculating a plurality of first SDs (starvation degrees) respectively for the first successive process nodes;
• calculating a plurality of second SDs respectively for the second successive process nodes;
• calculating first and second SFs (starvation factors) respectively contingent upon the first SDs and the second SDs;
• and
• determining one of the wafer lots contingent upon the first and second SFs thereof.

An electronic device is fabricated in a fabrication factory utilizing the method of semiconductor work-in-process (WIP) dispatch management method comprising using a computer to perform the steps of:

• acquiring information regarding a plurality of wafer lots to be processed in a process node by the computer;
• determining which wafer lot requires processing prior to the other wafer lots by analyzing a load of a plurality of successive process nodes for each wafer lots by the computer;
• and
• directing a transport system to transport the determined wafer lot to the process node by the computer,
• wherein the analyzed quantity of the successive process nodes corresponding to any of the wafer lots is determined by limiting a summation of cycle times of the successive process nodes to a predetermined observation time period.

A system of semiconductor WIP (work-in-process) dispatch management comprising:

• a transport system;
• and
• a dispatch management system coupling to the transportation system, acquiring information regarding a plurality of wafer lots to be processed in a process node, and determining which wafer lot requires processing prior to the other wafer lots by analyzing a load of a plurality of successive process nodes for each wafer lot, enabling to transport the determined wafer lot to the process node via the transport system,
• wherein the analyzed quantity of the successive process nodes corresponding to any of the wafer lots is determined by limiting a summation of cycle times of the successive process nodes to a predetermined observation time period.