Non-volatile memory and method with reduced source line bias errors

In a non-volatile memory device having a plurality of memory cells to be sensed in parallel, each memory cell having a source electrode, and the plurality of memory cells having their source electrodes coupled together into a combined source line, a read system comprising:

• a controller;
• and
• a plurality of sensing circuits for sensing said plurality of memory cells in parallel, each sensing circuit further comprising:
• a discriminator coupled to receive a conduction current of an associated memory cell, said discriminator discriminating whether the conduction current is higher or lower than a predetermined demarcation current value;
• a latch being set to register the associated memory cell in response to said discriminator identifying a conduction current higher than said predetermined demarcation current value;
• and
• an inhibitor being enabled by said latch being set to turn off the conduction current of the associated memory cell;
• and wherein
• said controller controls said plurality of sensing circuits to operate a predetermined number of times before reading out the determined memory state.

In a non-volatile memory device having a plurality of memory cells to be sensed in parallel, each memory cell having a source electrode, and the plurality of memory cells having their source electrodes coupled together into a combined source line, a read system comprising:

• a controlling means;
• and
• a plurality of sensing circuits for sensing conduction currents of said plurality of memory cells in parallel, each sensing circuit further comprising:
• means for discriminating whether the conduction current is higher or lower than a predetermined demarcation current value;
• means for registering the associated memory cell in response whenever its conduction current is identified to be higher than said predetermined demarcation current value;
• and
• means for inhibiting the associated memory cell with said higher conduction current;
• and wherein
• said controlling means operating said plurality of sensing circuits a predetermined number of times before reading out the sensed memory state in a final pass.