US 7,196,926 B1 · Vertical capacitor memory cell and its applications

Abstract

A capacitor memory is realized, wherein a capacitor stores data and a diode controls to store data “1” or “0”. Diode has four terminals wherein first terminal serves as word line, second terminal serves as storage node, third terminal is floating, fourth terminal serves as bit line, at least one of the terminals is formed vertically, which diode is formed from silicon, metal or compound materials. The cell is isolated from well or substrate, and the height of cell is close to that of control circuit. A capacitor plate couples to second terminal, which plate has no coupling region to first, third and fourth terminal. With no coupling, the inversion layer of plate in the storage node is isolated from the adjacent nodes. In doing so, the plate can swing ground level to positive supply level to write. As a result, no negative generator is required for controlling plate. Word line and bit line keep ground level during standby, and rise to supply level for read or write operation. In this manner, no holding current is required during standby, and operating current is dramatically reduced with no negative generator. Write has a sequence to clear the state of cell before writing to store data regardless of previous state. Refresh cycle is periodically asserted to sustain data. The present invention can be applied for destructive read, or for nondestructive read adding pull-down device to bit line.

Claims19

Dependent claims

A random access memory, comprising:

wherein a capacitor stores data and a diode controls to store data “1” or “0”;
diode has four terminals, wherein first terminal is p-type and serves as word line, second terminal is n-type and serves as storage node, third terminal is p-type and floating, and fourth terminal is n-type and serves as bit line;
plate of capacitor couples to storage node, which plate has no coupling region to first, third and fourth terminal;
and
single positive supply is used for memory operation;
during standby, word line and bit line stay at ground level, and plate stays at high level;
word line and bit line move to high level to read or write, and plate moves to ground level to write;
and
a write sequence to clear the state of diode which is to turn-on diode before writing;
to write data “0”, 1) word line goes up to high level, 2) plate goes down to ground level, 3) bit line goes up to high level, 4) plate returns to high level, which couples to storage node higher than supply level, 5) word line returns to ground level, and 6) finally bit line returns to ground level;
to write data “1”, 1) word line goes up to high level, 2) plate goes down to ground level, 3) plate returns to high level but it can not couple storage node, 4) finally word line returns to ground level, while bit line keeps near ground level.

8 more elements

Dependencies are inferred from the claim text.

Vertical capacitor memory cell and its applications

Life of this patent

Vertical capacitor memory cell and its applications

Life of this patent

Abstract

Claims19