Method and system for high-speed processing IPSec security protocol packets
AssigneeCorrent Corporation
InventorsLee P. Noehring, Chad W. Mercer, David Cassetti, Michael Privett, Satish Anand
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AssigneeCorrent Corporation
InventorsLee P. Noehring, Chad W. Mercer, David Cassetti, Michael Privett, Satish Anand
Estimating the term…
A packet processing system is embodied on an ASIC is optimized for processing IPSec security protocol packets in a hardware configuration. Embedded RISC processors operate with hardware support modules providing for IPSec packet processing at OC24 data rates and greater. IPSec packets are received through a streaming interface and buffered in an external memory. When the entire packet is in external memory, portions are buffered in a local memory for crypto-processing. As portions of the packets complete processing, the portions are buffered to an output portion of the external memory associated with the channel. When an entire packet competes processing, portions are buffered to a local memory for streaming. The hardware accordingly reduces the involvement of the RISC processors and significantly increases channel throughput providing for high-speed IPSec packet processing.
A security data packet processing system comprising:
A method for processing a security data packet comprising:
A method of processing an IPSec security protocol packet, the IPSec security protocol packet comprising an IPSec header, the method comprising:
An application specific integrated circuit for processing IPSec security protocol packets comprising:
A method of processing data packets for implementing a security protocol, the method comprising:
Dependencies are inferred from the claim text.