Complementary pass gate logic implementation of 64-bit arithmetic logic unit using propagate, generate, and kill
AssigneeSun Microsystems, Inc.
InventorsSanjay Dubey, Yoganand Chillarige, Shivakumar Sompur, Ban P. Wong, Cynthia Tran
Life of this patent
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Abstract
An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folded with local four-bit sums to efficiently generate a final sum output. The ALU implements ones complement subtraction by incorporating a subtraction select signal to invert each bit of a second operand. The ALU circuitry implements a push-pull methodology to improve performance.
Claims40
Arithmetic logic processing circuitry, comprising:
- a global carry chain implementing static propagate, kill, and generate circuitry, including,
- a first stage for generating first propagate, kill, and generate signals for each bit of a pair of multi-bit signal vectors;
- a second stage for generating second propagate, kill, and generate signals for a first group of the first propagate, kill, and generate signals;
- a third stage for generating third propagate, kill, and generate signals for a first group of the second propagate, kill, and generate signals;
- and
- a fourth stage for generating carry signals and carry complement signals, the fourth stage receiving inputs from each of the second stage and the third stage, the carry signals and the carry complement signals being useful for generating a sum result.
A method for making arithmetic logic processing circuitry, comprising:
- implementing a global carry chain using static propagate, kill, and generate circuitry, including,
- implementing a first stage for generating first propagate, kill, and generate signals for each bit of a pair of multi-bit signal vectors;
- implementing a second stage for generating second propagate, kill, and generate signals for a first group of the first propagate, kill, and generate signals;
- implementing a third stage for generating third propagate, kill, and generate signals for a first group of the second propagate, kill, and generate signals;
- and
- implementing a fourth stage for generating carry signals and carry complement signals, the fourth stage receiving inputs from each of the second stage and the third stage, the carry signals and the carry complement signals being useful for generating a sum result.
Arithmetic logic unit circuitry, comprising:
- a four-stage global carry chain implementing static propagate, kill, and generate circuitry for generating carry signals associated with a pair of multi-bit signal vectors, the carry signals being useful for generating a sum result for the pair of multi-bit signal vectors, wherein the carry signals include intermediate fourth-bit carry signals;
- and
- a summation processing circuit for creating sum and sum complement signals for each bit in the pair of multi-bit signal vectors, the summation processing circuit configured to generate local fourth-bit sum and sum complement signals, the summation processing circuit further configured to fold the local fourth-bit sum and sum complement signals with the intermediate fourth-bit carry signals to produce a final sum output signal vector.
Dependencies are inferred from the claim text.