Configurable interconnection of multiple different type functional units array including delay type for different instruction processing

An integrated circuit device, comprising a data processing block including:

• a plurality of operation units that are arranged in a first and second direction in a matrix, each operation unit including a flip-flop controlled with unit of clock;
• a plurality of first wire sets that extend in the first direction corresponding to an arrangement of the plurality of operation units in the first direction and transfer input data and/or output data of each of the operation units;
• a plurality of second wire sets that extend in the second direction corresponding to an arrangement of the plurality of operation units in the second direction and transfer input data and/or output data of each of the operation units;
• and
• a plurality of switching units that are positioned at each intersection between the first wire sets and the second wire sets and are capable of selecting and connecting any wire included in the first wire sets to any wire included in the second wire sets,
• wherein the plurality of operation units are sorted into a plurality of types of operation units that include different data paths that are suited to special-purpose processing, and operation units of the same type form an arrangement in the first direction or the second direction in at least part of the data processing block, and
• wherein the plurality of types of operation units includes a delay type operation unit that includes a data path suited to processing for delaying a transfer time of data and the delaying being adjustable in the unit of clock by information stored in a configuration memory.