Programmable logic device with on-chip nonvolatile user memory
AssigneeAltera Corporation
InventorsRafael C. Camarota, Tom White
Life of this patent
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Abstract
A programmable logic integrated circuit has user-accessible nonvolatile memory for use by the programmable logic. In a specific embodiment, the programmable logic integrated circuit has a programmable logic array portion and a nonvolatile memory array portion. The nonvolatile memory array portion is segregated into a boot data part and a user data partition. The boot data partition holds data for configuring the programmable logic portion on power up, and the user data partition is for use by the programmable logic. A user can store and retrieve data from the user data partition. A built-in oscillator can be programmably connected from the nonvolatile memory portion to the PLD portion.
Claims27
A programmable logic integrated circuit comprising:
- a programmable logic array portion of the programmable logic integrated circuit, comprising volatile memory elements, logic array blocks, and a programmable interconnect configurable using the volatile memory elements to implement user functions;
- and
- a nonvolatile memory portion of the programmable logic integrated circuit, coupled to the programmable logic array portion, wherein the nonvolatile memory portion comprises nonvolatile memory elements in a boot data partition to store configuration data for configuring the programmable logic array portion upon power-up of the programmable logic integrated circuit and a user data partition to store user data, wherein the nonvolatile memory portion comprises a first data port configured for data read access to the boot data partition and a second data port configured for data read access to the user data partition.
A method of operating a programmable integrated circuit comprising:
- after providing power to the programmable integrated circuit, transferring configuration data from a nonvolatile memory portion of the programmable integrated circuit through a read-only port of the nonvolatile memory portion to a programmable logic array portion of the programmable integrated circuit to configure the programmable logic array portion of the programmable integrated circuit;
- during a normal operation mode of the programmable integrated circuit, transferring data stored in a user data partition of the nonvolatile memory portion of the programmable integrated circuit to a volatile memory portion of the programmable logic array portion for use by the programmable logic array portion;
- and
- during the normal operation mode enabling a clock enable signal to activate an oscillator signal coupled to the nonvolatile portion, wherein the oscillator signal is configured to clock the user's data from the nonvolatile memory to the programmable array portion.
A programmable integrated circuit comprising:
- a programmable logic array block comprising programmable logic configured using volatile memory elements;
- an input/output block to input or output data;
- an input/output multiplexer coupled between the programmable logic array block and the input/output block;
- a nonvolatile memory array block comprising a plurality of nonvolatile memory cells partitioned in a boot data partition and a user data partition;
- and
- an interface block, coupled between the nonvolatile memory array block and the input/output multiplexer.
A programmable integrated circuit comprising:
- a programmable logic array portion of the programmable integrated circuit, comprising volatile memory elements, logic array blocks, and a programmable interconnect configurable using the volatile memory elements to implement user functions;
- a nonvolatile memory portion of the programmable integrated circuit, coupled to the programmable logic array portion, wherein the nonvolatile memory portion comprises nonvolatile memory elements in a boot data partition to store configuration data for configuring the programmable logic array portion upon power-up of the programmable integrated circuit and comprises nonvolatile memory elements in a user data partition to store user data for an operational mode where the user functions are being utilized, wherein the boot data partition is accessible to the programmable logic array portion through a first port and the user data partition is accessible to a user though another port;
- and
- an oscillator circuit programmably coupled to the programmable logic array portion of the integrated circuit and nonvolatile memory portion of the integrated circuit, wherein the oscillator circuit comprises an input for enabling and disabling the oscillator circuit.
Dependencies are inferred from the claim text.