Circuit layout methodology using a shape processing application

A method for developing or modifying a layout for fabricating a very large scale integrated circuit (IC) (VLSI), in a plurality of different layers having a plurality of masks for the different layers, in a given IC technology with a set of reduced ground rules for layout grids for the plurality of different layers, wherein the size of an increment in a layout grid represents the smallest dimension that can be used by a designer in layout data, comprising:

• classifying the plurality of masks into different groups based upon whether they are (a) used to provide vertical connections between vertically adjacent layers, or (b) used for horizontal patterning, or (c) used to pattern alignment aids;
• depending upon which group a mask is classified into, using design rules for the given IC technology to establish a layer-specific layout grid increment value for that mask, to develop a plurality of layer-specific layout grid increment values for the plurality of masks;
• using a layout-optimization application to scale data and select the size of the layout grid increment value for at least some of the plurality of different layers of the VLSI layout;
• using a layout-optimization application to select minimum line widths and minimum line spaces for at least some of the plurality of different layers of the VLSI layout;
• using a shape-processing application to select via sizes, via locations, and via borders for at least some of the plurality of different layers of the VLSI layout.