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US 7,188,284 B2Granted
Error detecting circuit
AssigneeIntel Corporation
InventorsSubhasish Mitra, Kee S. Kim, Tak M. Mak, Prashant M. Goteti
Life of this patent
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Abstract
In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.
Claims28
An apparatus, comprising:
- a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal;
- a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation;
- and
- an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.
1 more element
A system, comprising:
- an integrated circuit package including a chip having a plurality of scan cells;
- each of the scan cells including:
- a datapath circuit including at least one datapath latch to generate a data output signal in response to a data input signal and a first data clock signal;
- a shadow circuit including at least one shadow latch to generate a shadow output signal in response to the data input signal and the first data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and a first test clock signal during a test mode of operation;
- and
- an error detect element, having a pair of input terminals coupled to a pair of output terminals of the at least one datapath latch and the at least one shadow latch, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal during the functional mode of operation;
- and
- a bus with the integrated circuit package coupled thereto;
- and
- a mass storage device coupled to the bus.
7 more elements
An apparatus, comprising:
- a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal, with the datapath circuit including at least one datapath latch;
- a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal, with the shadow circuit including at least one shadow latch;
- an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal;
- a storage circuit, coupled to the error detect circuit, to store the error signal;
- the storage circuit including the shadow circuit and a feedback circuit, with the feedback circuit having an input coupled to the output of the error detect circuit and an output coupled to an input of the shadow circuit to provide the error signal to the shadow circuit to be stored;
- and
- a read-out circuit, coupled to the storage circuit, to move the error signal from the storage circuit.
4 more elements
An apparatus, comprising:
- a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal;
- a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal;
- an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal;
- a storage circuit, coupled to the error detect circuit, to store the error signal;
- and
- a read-out circuit, coupled to the storage circuit, to move the error signal from the storage circuit, and
- wherein the shadow circuit includes at least one shadow latch to generate a shadow output signal in response to the data input signal and the first data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and a first test clock signal during a test mode of operation.
4 more elements
Dependencies are inferred from the claim text.